Simulation Results: edn/edn1

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.30 %
  • code
  • 82.57 %
  • assert
  • 97.14 %
  • func
  • 79.20 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.85 %
  • toggle
  • 87.23 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 17.702us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.110s 55.744us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.110s 59.393us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.590s 337.670us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 23.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 21.202us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.110s 59.393us 1 1 100.00
edn_csr_aliasing 1.080s 23.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.110s 60.642us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.110s 60.642us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.110s 60.642us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.120s 41.883us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.390s 27.689us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 42.009us 1 1 100.00
disable 2 2 100.00
edn_disable 1.120s 13.896us 1 1 100.00
edn_disable_auto_req_mode 1.220s 19.998us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.360s 43.194us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.950s 21.874us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.040s 60.285us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.800s 454.410us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.800s 454.410us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.110s 55.744us 1 1 100.00
edn_csr_rw 1.110s 59.393us 1 1 100.00
edn_csr_aliasing 1.080s 23.772us 1 1 100.00
edn_same_csr_outstanding 1.240s 72.419us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.110s 55.744us 1 1 100.00
edn_csr_rw 1.110s 59.393us 1 1 100.00
edn_csr_aliasing 1.080s 23.772us 1 1 100.00
edn_same_csr_outstanding 1.240s 72.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
edn_tl_intg_err 1.510s 50.815us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.120s 18.639us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.390s 27.689us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.390s 27.689us 1 1 100.00
edn_sec_cm 3.410s 233.873us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.390s 27.689us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.510s 50.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 42.350s 1750.125us 1 1 100.00