Simulation Results: entropy_src/rng_4bits

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 73.49 %
  • code
  • 87.09 %
  • assert
  • 83.91 %
  • func
  • 49.47 %
  • block
  • 94.17 %
  • line
  • 97.01 %
  • branch
  • 85.93 %
  • toggle
  • 75.86 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 101.270us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 49.176us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 66.438us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 18.000s 1862.487us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 22.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 31.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 66.438us 1 1 100.00
entropy_src_csr_aliasing 2.000s 22.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 101.270us 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
entropy_src_fw_ov 3602.060s 0.000us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 3602.060s 0.000us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 205.000s 13198.071us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
entropy_src_intr 3.000s 55.776us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
entropy_src_functional_alerts 6.000s 183.039us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 205.000s 13477.955us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 36.492us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 22.658us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 51.174us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 477.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 477.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 49.176us 1 1 100.00
entropy_src_csr_rw 2.000s 66.438us 1 1 100.00
entropy_src_csr_aliasing 2.000s 22.544us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 30.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 49.176us 1 1 100.00
entropy_src_csr_rw 2.000s 66.438us 1 1 100.00
entropy_src_csr_aliasing 2.000s 22.544us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 30.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 118.638us 1 1 100.00
entropy_src_tl_intg_err 4.000s 398.494us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
entropy_src_cfg_regwen 2.000s 23.175us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
entropy_src_fw_ov 3602.060s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
entropy_src_sec_cm 3.000s 118.638us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
entropy_src_sec_cm 3.000s 118.638us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 93.000s 13237.571us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
entropy_src_sec_cm 3.000s 118.638us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
entropy_src_sec_cm 3.000s 118.638us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 57.588us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 183.039us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 398.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 259.000s 14096.709us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 19.000s 3150.971us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 111774633953081214511076004471896675654068365016030719851213993385600141761735 730
UVM_INFO @ 3150971182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
entropy_src_fw_ov 54207809395395648359152077865009448639770881972740216545098599710939394392347 None