Simulation Results: hmac

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.60 %
  • code
  • 87.45 %
  • assert
  • 96.29 %
  • func
  • 43.05 %
  • line
  • 99.59 %
  • branch
  • 98.70 %
  • cond
  • 95.74 %
  • toggle
  • 46.17 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 13.790s 3670.723us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.940s 22.014us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.990s 15.864us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.520s 277.599us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.030s 17.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.720s 49.655us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.990s 15.864us 1 1 100.00
hmac_csr_aliasing 1.030s 17.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 32.240s 7576.465us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 48.110s 4050.092us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 217.300s 8287.602us 1 1 100.00
hmac_test_sha384_vectors 374.410s 15939.112us 1 1 100.00
hmac_test_sha512_vectors 25.950s 326.153us 1 1 100.00
hmac_test_hmac256_vectors 13.970s 1821.694us 1 1 100.00
hmac_test_hmac384_vectors 13.920s 899.647us 1 1 100.00
hmac_test_hmac512_vectors 11.950s 1116.148us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.080s 9964.352us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 852.700s 7092.348us 1 1 100.00
error 1 1 100.00
hmac_error 85.260s 33863.463us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 161.730s 19204.927us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 13.790s 3670.723us 1 1 100.00
hmac_long_msg 32.240s 7576.465us 1 1 100.00
hmac_back_pressure 48.110s 4050.092us 1 1 100.00
hmac_datapath_stress 852.700s 7092.348us 1 1 100.00
hmac_burst_wr 19.080s 9964.352us 1 1 100.00
hmac_stress_all 1244.120s 122304.989us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 13.790s 3670.723us 1 1 100.00
hmac_long_msg 32.240s 7576.465us 1 1 100.00
hmac_back_pressure 48.110s 4050.092us 1 1 100.00
hmac_datapath_stress 852.700s 7092.348us 1 1 100.00
hmac_wipe_secret 161.730s 19204.927us 1 1 100.00
hmac_test_sha256_vectors 217.300s 8287.602us 1 1 100.00
hmac_test_sha384_vectors 374.410s 15939.112us 1 1 100.00
hmac_test_sha512_vectors 25.950s 326.153us 1 1 100.00
hmac_test_hmac256_vectors 13.970s 1821.694us 1 1 100.00
hmac_test_hmac384_vectors 13.920s 899.647us 1 1 100.00
hmac_test_hmac512_vectors 11.950s 1116.148us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 13.790s 3670.723us 1 1 100.00
hmac_long_msg 32.240s 7576.465us 1 1 100.00
hmac_back_pressure 48.110s 4050.092us 1 1 100.00
hmac_datapath_stress 852.700s 7092.348us 1 1 100.00
hmac_burst_wr 19.080s 9964.352us 1 1 100.00
hmac_error 85.260s 33863.463us 1 1 100.00
hmac_wipe_secret 161.730s 19204.927us 1 1 100.00
hmac_test_sha256_vectors 217.300s 8287.602us 1 1 100.00
hmac_test_sha384_vectors 374.410s 15939.112us 1 1 100.00
hmac_test_sha512_vectors 25.950s 326.153us 1 1 100.00
hmac_test_hmac256_vectors 13.970s 1821.694us 1 1 100.00
hmac_test_hmac384_vectors 13.920s 899.647us 1 1 100.00
hmac_test_hmac512_vectors 11.950s 1116.148us 1 1 100.00
hmac_stress_all 1244.120s 122304.989us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1244.120s 122304.989us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.820s 58.543us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.890s 12.304us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.220s 62.773us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.220s 62.773us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.940s 22.014us 1 1 100.00
hmac_csr_rw 0.990s 15.864us 1 1 100.00
hmac_csr_aliasing 1.030s 17.801us 1 1 100.00
hmac_same_csr_outstanding 2.540s 518.744us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.940s 22.014us 1 1 100.00
hmac_csr_rw 0.990s 15.864us 1 1 100.00
hmac_csr_aliasing 1.030s 17.801us 1 1 100.00
hmac_same_csr_outstanding 2.540s 518.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.220s 286.179us 1 1 100.00
hmac_tl_intg_err 4.380s 381.978us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.380s 381.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 13.790s 3670.723us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.570s 1563.253us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 334.380s 175601.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.480s 22.333us 1 1 100.00