Simulation Results

Simulation Results: i2c

27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
85.37 %

code
78.32 %

assert
97.25 %

func
80.55 %

line
96.38 %

branch
92.26 %

cond
85.04 %

toggle
73.87 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	20.270s	1646.232us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.730s	2647.163us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.950s	51.615us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.050s	30.875us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.330s	315.298us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	0.920s	72.731us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.620s	32.283us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.050s	30.875us	1	1	100.00
	i2c_csr_aliasing	0.920s	72.731us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.950s	16.075us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	30.080s	4470.835us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	162.150s	5399.795us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.950s	51.162us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	69.910s	8186.814us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	37.080s	1629.462us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.220s	78.023us	1	1	100.00
	i2c_host_fifo_fmt_empty	10.540s	1653.674us	1	1	100.00
	i2c_host_fifo_reset_rx	9.160s	379.913us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	73.610s	4288.298us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	34.260s	884.702us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	3.990s	199.049us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.220s	840.658us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	28.150s	25342.130us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.430s	2005.079us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	6.850s	410.674us	1	1	100.00
	i2c_target_intr_smoke	7.020s	2626.861us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.220s	122.959us	1	1	100.00
	i2c_target_fifo_reset_tx	1.410s	720.574us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	71.060s	36075.730us	1	1	100.00
	i2c_target_stress_rd	6.850s	410.674us	1	1	100.00
	i2c_target_intr_stress_wr	1.990s	508.594us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.060s	1079.309us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.580s	2036.526us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.720s	1988.615us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.320s	1774.088us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.880s	527.223us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.180s	87.352us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	162.150s	5399.795us	1	1	100.00
	i2c_host_perf_precise	3.320s	132.828us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	34.260s	884.702us	1	1	100.00
target_mode_tx_stretch_ctrl				0	1	0.00
	i2c_target_tx_stretch_ctrl	1.670s	48.076us	0	1	0.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.060s	520.540us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.270s	919.685us	1	1	100.00
	i2c_target_nack_txstretch	1.740s	128.653us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.970s	1504.655us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.860s	1600.277us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.970s	20.519us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.040s	34.439us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.550s	24.759us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.550s	24.759us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	51.615us	1	1	100.00
	i2c_csr_rw	1.050s	30.875us	1	1	100.00
	i2c_csr_aliasing	0.920s	72.731us	1	1	100.00
	i2c_same_csr_outstanding	1.150s	132.621us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	51.615us	1	1	100.00
	i2c_csr_rw	1.050s	30.875us	1	1	100.00
	i2c_csr_aliasing	0.920s	72.731us	1	1	100.00
	i2c_same_csr_outstanding	1.150s	132.621us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.540s	56.700us	1	1	100.00
	i2c_sec_cm	1.030s	222.725us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.540s	56.700us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	38.220s	1068.951us	1
target_error_intr				1
	i2c_target_unexp_stop	1.330s	60.714us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	22.930s	2679.755us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	90229288063581202127367734873219418896651749754107238784177181071169068383868	86	UVM_INFO @ 16074598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	78289849835443573394212862374162313869606545697357298378651090277548320685250	97	UVM_INFO @ 4470835215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	28816225026510346839291424704873262063231023551702850305402405416065812764882	126	UVM_INFO @ 2679754739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	81061613155615087002004312000233117362780983885898181578864368522622381554351	90	UVM_INFO @ 840658298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	60767952355929095549062309747613649827127845847676249995741422065454872756522	84	UVM_INFO @ 60713790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	31820365426456971653444607321223988317485377372478115018937147060294932387238	103	UVM_INFO @ 1068950622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	45587971877954545150681365101525192383682194092699039376427469369556961322519	91	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @143027
Error-[CNST-CIF] Constraints inconsistency failure				1 test run
	i2c_target_tx_stretch_ctrl	69912545802184468449104184233649709108597135874862505337227103988892850434834	127	src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.