Simulation Results: keymgr_dpe/earlgrey

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 64.77 %
  • code
  • 82.57 %
  • assert
  • 97.21 %
  • func
  • 14.53 %
  • line
  • 97.48 %
  • branch
  • 93.67 %
  • cond
  • 86.55 %
  • toggle
  • 59.49 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 9.050s 980.742us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.190s 62.320us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.260s 17.760us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 6.960s 955.466us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.490s 26.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.410s 58.018us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.260s 17.760us 1 1 100.00
keymgr_dpe_csr_aliasing 1.490s 26.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 1.000s 85.684us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.020s 21.726us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.530s 246.027us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.530s 246.027us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.190s 62.320us 1 1 100.00
keymgr_dpe_csr_rw 1.260s 17.760us 1 1 100.00
keymgr_dpe_csr_aliasing 1.490s 26.357us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.220s 546.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.190s 62.320us 1 1 100.00
keymgr_dpe_csr_rw 1.260s 17.760us 1 1 100.00
keymgr_dpe_csr_aliasing 1.490s 26.357us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.220s 546.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 8.710s 711.641us 1 1 100.00
keymgr_dpe_tl_intg_err 4.290s 108.191us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.100s 120.292us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.100s 120.292us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.100s 120.292us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.100s 120.292us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 3.110s 119.822us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 8.710s 711.641us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 8.710s 711.641us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 7581194527031030822591699278175293759079429862991696523284922655953391772282 83
UVM_ERROR @ 120291885 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 120291885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 57447069860714774229913436648680088093807462308919957285133556589465822862845 83
UVM_ERROR @ 119822073 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 119822073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---