Simulation Results: kmac/unmasked

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 78.40 %
  • code
  • 63.68 %
  • assert
  • 94.45 %
  • func
  • 77.07 %
  • line
  • 95.50 %
  • branch
  • 88.21 %
  • cond
  • 82.55 %
  • toggle
  • 21.49 %
  • FSM
  • 30.66 %
Validation stages
V1
100.00%
V2
72.41%
V2S
62.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 39.520s 14019.322us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.140s 268.530us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.080s 19.772us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 22.020s 1837.077us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 1.220s 24.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.440s 58.244us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.080s 19.772us 1 1 100.00
kmac_csr_aliasing 1.220s 24.813us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.890s 64.183us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.430s 60.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2513.220s 117885.205us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 880.680s 82944.597us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 37.710s 11553.558us 1 1 100.00
kmac_test_vectors_sha3_256 1347.180s 99680.283us 1 1 100.00
kmac_test_vectors_sha3_384 29.980s 3532.635us 1 1 100.00
kmac_test_vectors_sha3_512 1031.100s 58315.700us 1 1 100.00
kmac_test_vectors_shake_128 217.480s 58953.621us 1 1 100.00
kmac_test_vectors_shake_256 2189.880s 111060.148us 1 1 100.00
kmac_test_vectors_kmac 2.040s 126.724us 1 1 100.00
kmac_test_vectors_kmac_xof 2.850s 800.352us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 111.940s 5573.989us 1 1 100.00
app 0 1 0.00
kmac_app 3.880s 137.635us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 7.330s 703.967us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 2.470s 107.153us 0 1 0.00
error 1 1 100.00
kmac_error 51.060s 1147.091us 1 1 100.00
key_error 0 1 0.00
kmac_key_error 1.080s 5.212us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.080s 12.640us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 22.490s 523.596us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 18.490s 14532.044us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.020s 8.380us 0 1 0.00
lc_escalation 0 1 0.00
kmac_lc_escalation 1.170s 54.237us 0 1 0.00
stress_all 0 1 0.00
kmac_stress_all 57.730s 8072.145us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 1.020s 27.681us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.920s 14.733us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.250s 326.634us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.250s 326.634us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.140s 268.530us 1 1 100.00
kmac_csr_rw 1.080s 19.772us 1 1 100.00
kmac_csr_aliasing 1.220s 24.813us 1 1 100.00
kmac_same_csr_outstanding 2.820s 110.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.140s 268.530us 1 1 100.00
kmac_csr_rw 1.080s 19.772us 1 1 100.00
kmac_csr_aliasing 1.220s 24.813us 1 1 100.00
kmac_same_csr_outstanding 2.820s 110.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 37.480us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.440s 37.480us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 37.480us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.440s 37.480us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.570s 50.289us 1 1 100.00
tl_intg_err 1 2 50.00
kmac_sec_cm 1.410s 90.972us 0 1 0.00
kmac_tl_intg_err 3.200s 227.844us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.200s 227.844us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
kmac_lc_escalation 1.170s 54.237us 0 1 0.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 39.520s 14019.322us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 111.940s 5573.989us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.440s 37.480us 1 1 100.00
sec_cm_fsm_sparse 0 1 0.00
kmac_sec_cm 1.410s 90.972us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
kmac_sec_cm 1.410s 90.972us 0 1 0.00
sec_cm_packer_ctr_redun 0 1 0.00
kmac_sec_cm 1.410s 90.972us 0 1 0.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 39.520s 14019.322us 1 1 100.00
sec_cm_fsm_global_esc 0 1 0.00
kmac_lc_escalation 1.170s 54.237us 0 1 0.00
sec_cm_fsm_local_esc 0 1 0.00
kmac_sec_cm 1.410s 90.972us 0 1 0.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 1.980s 43.091us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 39.520s 14019.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 41.090s 2218.148us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (kmac_scoreboard.sv:524) scoreboard [scoreboard] Saw request be handled for app * when that app was not selected. 7 test runs
kmac_app 13516010379648558172529910382057823026521677237730011647681852224950658128474 79
UVM_INFO @ 137635336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 81094467285468282128137474515417238160453025651864007571743989495656525410306 79
UVM_INFO @ 703967096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 33264572461766310198078114777067526937482400347045074016043040757503896907184 78
UVM_INFO @ 107153061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_mubi 14771846085705659232587983464508050774221724648027701410722416494146995216733 78
UVM_INFO @ 43091045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 4419752213325953586739412336810732332999671184666635544178215906284286979930 77
UVM_INFO @ 5211526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 98654411170515783803354867662656825695307729486537659522724763538953229475347 77
UVM_INFO @ 8379637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 15512170703564759678241519395125161420024390920371697394974025111232599194415 118
UVM_INFO @ 8072144717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). 2 test runs
kmac_lc_escalation 65916665656278597415289331738000296484667615273604551873113754908586356651030 77
UVM_INFO @ 54237190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sec_cm 11937584937130301883452055458127846246393493850207404131224547892950042801855 79
UVM_INFO @ 90972149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 1 test run
kmac_sideload_invalid 90174132096993872218502339804258038641975240671053112648903255144438790544653 76
UVM_INFO @ 12640166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 24079486720802943499842932551515693912430092457597190788257720159330667966115 151
UVM_INFO @ 2218148058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---