Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.01 %
  • code
  • 84.52 %
  • assert
  • 94.41 %
  • func
  • 94.09 %
  • line
  • 97.20 %
  • branch
  • 93.76 %
  • cond
  • 79.59 %
  • toggle
  • 86.65 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.610s 40.646us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.110s 17.820us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.080s 14.448us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 229.551us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 13.099us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 48.416us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.080s 14.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 13.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.700s 125.455us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.200s 2422.732us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 13.963us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.900s 100.752us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.930s 611.122us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_prog_failure 1.900s 100.752us 1 1 100.00
lc_ctrl_errors 3.930s 611.122us 1 1 100.00
lc_ctrl_security_escalation 3.990s 358.421us 1 1 100.00
lc_ctrl_jtag_state_failure 24.390s 7979.948us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.070s 810.146us 1 1 100.00
lc_ctrl_jtag_errors 19.070s 5584.325us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.230s 641.575us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.030s 8278.741us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.070s 810.146us 1 1 100.00
lc_ctrl_jtag_errors 19.070s 5584.325us 1 1 100.00
lc_ctrl_jtag_access 4.680s 1356.375us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.120s 1169.986us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.110s 155.495us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.970s 152.481us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.050s 668.697us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.810s 580.052us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.840s 208.490us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.870s 114.796us 1 1 100.00
lc_ctrl_jtag_alert_test 1.270s 45.390us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.970s 416.264us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.790s 46.511us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 94.240s 26595.559us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.380s 118.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.080s 163.622us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.080s 163.622us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 17.820us 1 1 100.00
lc_ctrl_csr_rw 1.080s 14.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 13.099us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.690s 75.818us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 17.820us 1 1 100.00
lc_ctrl_csr_rw 1.080s 14.448us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 13.099us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.690s 75.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 275.016us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 275.016us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.200s 2422.732us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 690.474us 1 1 100.00
lc_ctrl_sec_cm 5.510s 465.385us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.990s 358.421us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.700s 125.455us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.030s 8278.741us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 717.750us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 717.750us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.480s 406.833us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.130s 331.166us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.130s 331.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 25.700s 1932.822us 1 1 100.00