Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.05 %
  • code
  • 84.02 %
  • assert
  • 94.55 %
  • func
  • 91.58 %
  • line
  • 97.17 %
  • branch
  • 93.57 %
  • cond
  • 79.15 %
  • toggle
  • 86.66 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.720s 75.233us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 17.493us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.720us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.300s 48.910us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.150s 12.916us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.310s 104.525us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 15.720us 1 1 100.00
lc_ctrl_csr_aliasing 1.150s 12.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.650s 71.484us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.580s 662.801us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.910s 44.809us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.940s 66.771us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.950s 236.251us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_prog_failure 1.940s 66.771us 1 1 100.00
lc_ctrl_errors 3.950s 236.251us 1 1 100.00
lc_ctrl_security_escalation 2.870s 1368.401us 1 1 100.00
lc_ctrl_jtag_state_failure 12.300s 808.283us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.570s 414.507us 1 1 100.00
lc_ctrl_jtag_errors 13.050s 2087.864us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.870s 977.108us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.820s 567.353us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.570s 414.507us 1 1 100.00
lc_ctrl_jtag_errors 13.050s 2087.864us 1 1 100.00
lc_ctrl_jtag_access 1.100s 64.384us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.550s 1277.905us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.060s 96.430us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.940s 72.217us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.060s 676.349us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.660s 646.458us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 58.506us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.730s 102.696us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 553.294us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.300s 69.392us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.140s 14.265us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 168.980s 11749.318us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 30.206us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.950s 147.012us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.950s 147.012us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 17.493us 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.720us 1 1 100.00
lc_ctrl_csr_aliasing 1.150s 12.916us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 51.668us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 17.493us 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.720us 1 1 100.00
lc_ctrl_csr_aliasing 1.150s 12.916us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 51.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 67.746us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 67.746us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.580s 662.801us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.920s 167.270us 1 1 100.00
lc_ctrl_sec_cm 5.910s 1049.795us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.870s 1368.401us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.650s 71.484us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.820s 567.353us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.780s 2253.797us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.780s 2253.797us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.400s 757.365us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.530s 1414.708us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.530s 1414.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 64.130s 5124.294us 1 1 100.00