Simulation Results: otbn

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.02 %
  • code
  • 86.17 %
  • assert
  • 89.86 %
  • func
  • 97.03 %
  • block
  • 99.23 %
  • line
  • 99.44 %
  • branch
  • 94.43 %
  • toggle
  • 84.62 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 44.222us 1 1 100.00
otbn_smoke_vectorized 8.000s 40.312us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 24.909us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 10.000s 23.849us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 14.000s 51.965us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 28.000s 15.429us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 28.000s 44.304us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 10.000s 23.849us 1 1 100.00
otbn_csr_aliasing 28.000s 15.429us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 72.000s 792.709us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 42.000s 1247.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 51.000s 144.910us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 89.000s 167.470us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 91.000s 267.734us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 55.000s 135.212us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 10.000s 91.689us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 11.000s 29.850us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 19.000s 33.215us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 69.446us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 11.000s 40.873us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 43.256us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 43.256us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 24.909us 1 1 100.00
otbn_csr_rw 10.000s 23.849us 1 1 100.00
otbn_csr_aliasing 28.000s 15.429us 1 1 100.00
otbn_same_csr_outstanding 7.000s 18.999us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 24.909us 1 1 100.00
otbn_csr_rw 10.000s 23.849us 1 1 100.00
otbn_csr_aliasing 28.000s 15.429us 1 1 100.00
otbn_same_csr_outstanding 7.000s 18.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 18.087us 1 1 100.00
otbn_dmem_err 9.000s 43.510us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 14.000s 231.735us 1 1 100.00
otbn_controller_ispr_rdata_err 17.000s 207.092us 1 1 100.00
otbn_mac_bignum_acc_err 23.000s 69.507us 1 1 100.00
otbn_urnd_err 11.000s 48.013us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 17.000s 17.453us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 18.000s 22.302us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 10.000s 181.132us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
otbn_tl_intg_err 15.000s 66.660us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 64.000s 810.028us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 44.222us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 43.510us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 18.087us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 66.660us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 91.689us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.087us 1 1 100.00
otbn_dmem_err 9.000s 43.510us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 29.850us 1 1 100.00
otbn_illegal_mem_acc 17.000s 17.453us 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.087us 1 1 100.00
otbn_dmem_err 9.000s 43.510us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 29.850us 1 1 100.00
otbn_illegal_mem_acc 17.000s 17.453us 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 91.689us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.087us 1 1 100.00
otbn_dmem_err 9.000s 43.510us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 29.850us 1 1 100.00
otbn_illegal_mem_acc 17.000s 17.453us 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 20.000s 13.448us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 12.000s 26.881us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 87.000s 1161.100us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 87.000s 1161.100us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 13.511us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 100.819us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 14.429us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 14.429us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 17.451us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 91.000s 267.734us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 73.239us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 18.084us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 411.000s 6050.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 222.000s 1169.730us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 13558120528850268777770032397546105849433505406654859547587676587510271196453 356
UVM_INFO @ 1169730145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 82218424645746908818159244504138223337015295138433518975410587276893303959697 113
UVM_ERROR @ 48013424 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 48013424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---