Simulation Results: otp_ctrl

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.48 %
  • code
  • 77.99 %
  • assert
  • 94.44 %
  • func
  • 72.02 %
  • line
  • 88.90 %
  • branch
  • 84.54 %
  • cond
  • 92.59 %
  • toggle
  • 80.15 %
  • FSM
  • 43.75 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.060s 52.366us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.020s 113.039us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.320s 46.125us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.450s 1179.064us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 1.810s 118.131us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.800s 304.888us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.320s 46.125us 1 1 100.00
otp_ctrl_csr_aliasing 1.810s 118.131us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.480s 553.643us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.770s 73.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.930s 3256.385us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 7.070s 3162.888us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 14.590s 1375.594us 1 1 100.00
otp_ctrl_check_fail 11.510s 3463.959us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.860s 327.855us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 23.570s 1510.848us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.630s 1377.896us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 32.770s 3900.578us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.890s 779.779us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 4.360s 1061.247us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 43.650s 6206.695us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.300s 110.099us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.680s 178.578us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.340s 121.266us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.340s 121.266us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.020s 113.039us 1 1 100.00
otp_ctrl_csr_rw 1.320s 46.125us 1 1 100.00
otp_ctrl_csr_aliasing 1.810s 118.131us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.770s 88.812us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.020s 113.039us 1 1 100.00
otp_ctrl_csr_rw 1.320s 46.125us 1 1 100.00
otp_ctrl_csr_aliasing 1.810s 118.131us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.770s 88.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
otp_ctrl_tl_intg_err 8.080s 1326.933us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.080s 1326.933us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_macro_errs 3.890s 779.779us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_macro_errs 3.890s 779.779us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.440s 2974.282us 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 7.070s 3162.888us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 11.510s 3463.959us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.370s 503.747us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 124.220s 22414.598us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.860s 327.855us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.160s 403.764us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.890s 779.779us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.370s 3650.718us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 38.260s 4170.986us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 13746318078643982794811123448357300918262130994983515681566066291048071141004 1956
UVM_INFO @ 779779232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_stress_all 67062032345856131834594298436588590760232550824408589934301351367289232365896 16329
UVM_INFO @ 6206694962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---