Simulation Results: pwrmgr

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.31 %
  • code
  • 94.64 %
  • assert
  • 97.91 %
  • func
  • 96.38 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 42.469us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.770s 30.925us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.690s 349.056us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 18.630us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.710s 95.775us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 18.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.840s 124.433us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.840s 124.433us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.180s 202.424us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 82.517us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.060s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.770s 178.795us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.060s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.020s 191.766us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.710s 36.017us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.790s 66.626us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.032s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 83.395us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.310s 61.045us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.310s 61.045us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.770s 30.925us 1 1 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 18.630us 1 1 100.00
pwrmgr_same_csr_outstanding 1.000s 73.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.770s 30.925us 1 1 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 18.630us 1 1 100.00
pwrmgr_same_csr_outstanding 1.000s 73.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.029s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.029s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.070s 800.572us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.020s 191.766us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.240s 792.277us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.870s 73.956us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.710s 30.129us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 36.496us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.026s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.990s 204.629us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.810s 41.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.760s 98.546us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.950s 2201.806us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
pwrmgr_glitch 26391574775735294498404552004036217522204637999993382420848551555221772873984 None
pwrmgr_tl_intg_err 51284698882118729013098795233291806313330657998617417149928610166263809102284 None
pwrmgr_sec_cm 26038080929788295558246071862587105851537779047968249253370417030865163353626 None
pwrmgr_stress_all 111159125413420729099935252472056296666625342513847302291200444346843064218592 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 109260782344992740283614578864227159681061985858256110763898175571567685331272 167
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 73157688963313517999375366545646346126428056325747191991955148016597945407653 85
UVM_ERROR @ 98546054 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98546054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---