Simulation Results: rom_ctrl/192kb

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 92.74 %
  • assert
  • 97.53 %
  • func
  • 96.64 %
  • line
  • 98.95 %
  • branch
  • 98.56 %
  • cond
  • 97.77 %
  • toggle
  • 95.10 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 19.690s 1038.707us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 29.730s 77.783us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 12.200s 52.553us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 12.310s 116.274us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 10.840s 55.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.690s 71.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 12.200s 52.553us 1 1 100.00
rom_ctrl_csr_aliasing 10.840s 55.355us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 14.430s 73.716us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.500s 51.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 10.470s 30.420us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 76.660s 3129.886us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 27.900s 1078.948us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 10.380s 94.496us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 11.860s 75.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 11.860s 75.223us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 29.730s 77.783us 1 1 100.00
rom_ctrl_csr_rw 12.200s 52.553us 1 1 100.00
rom_ctrl_csr_aliasing 10.840s 55.355us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.430s 118.240us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 29.730s 77.783us 1 1 100.00
rom_ctrl_csr_rw 12.200s 52.553us 1 1 100.00
rom_ctrl_csr_aliasing 10.840s 55.355us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.430s 118.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 41.780s 78.105us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
rom_ctrl_tl_intg_err 193.620s 171.270us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 19.690s 1038.707us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 19.690s 1038.707us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 19.690s 1038.707us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 193.620s 171.270us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
rom_ctrl_kmac_err_chk 27.900s 1078.948us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 313.100s 14967.053us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 41.780s 78.105us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 862.520s 234.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 56.070s 50799.867us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 43436025736224196862754813027723124656243654143970733540474010094152435303296 85
UVM_INFO @ 30420372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---