Simulation Results: rv_timer

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.49 %
  • code
  • 94.66 %
  • assert
  • 97.45 %
  • func
  • 97.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.810s 636.997us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.590s 13.024us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 68.475us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.060s 91.423us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.690s 12.145us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.700s 24.153us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 68.475us 1 1 100.00
rv_timer_csr_aliasing 0.690s 12.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.890s 112.912us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.850s 1446.439us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 137.890s 505302.344us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 137.890s 505302.344us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.410s 8365.257us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.660s 14.768us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 111.263us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.170s 896.288us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.170s 896.288us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 13.024us 1 1 100.00
rv_timer_csr_rw 0.600s 68.475us 1 1 100.00
rv_timer_csr_aliasing 0.690s 12.145us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 97.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 13.024us 1 1 100.00
rv_timer_csr_rw 0.600s 68.475us 1 1 100.00
rv_timer_csr_aliasing 0.690s 12.145us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 97.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.880s 213.202us 1 1 100.00
rv_timer_tl_intg_err 0.950s 358.614us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.950s 358.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.600s 62.792us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 151.170us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 21.010s 3499.778us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 13739732775952315153162015157117005616851271113526840992119997946632058193781 81
UVM_INFO @ 62791900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 99478652658924585541078294923295898621957480738674365179731748651551535550808 82
UVM_INFO @ 151170001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---