Simulation Results: spi_device/1r1w

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.82 %
  • code
  • 91.19 %
  • assert
  • 95.40 %
  • func
  • 76.88 %
  • line
  • 98.87 %
  • branch
  • 98.20 %
  • cond
  • 95.52 %
  • toggle
  • 73.99 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 132.040s 40262.546us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.820s 75.310us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.140s 42.465us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.030s 2985.015us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.980s 413.807us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.650s 55.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.140s 42.465us 1 1 100.00
spi_device_csr_aliasing 1.980s 413.807us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.740s 91.985us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.990s 200.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 40.195us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.810s 7.118us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.810s 3.660us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.820s 1097.407us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.820s 1097.407us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.450s 2546.968us 1 1 100.00
spi_device_tpm_sts_read 0.730s 23.743us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.860s 4880.240us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 19.290s 20493.166us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.850s 8573.489us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.850s 8573.489us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.050s 400.004us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.050s 400.004us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.050s 400.004us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.050s 400.004us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.050s 400.004us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.460s 2277.179us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 13.260s 2469.624us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 13.260s 2469.624us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 13.260s 2469.624us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.460s 2208.232us 1 1 100.00
spi_device_read_buffer_direct 8.430s 6262.079us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 13.260s 2469.624us 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 26.730s 11998.083us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 20.040s 2614.963us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 20.040s 2614.963us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 88.140s 81178.772us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 132.040s 40262.546us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 84.920s 22886.399us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 157.680s 114213.333us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.710s 22.315us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 45.675us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.050s 71.389us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.050s 71.389us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 75.310us 1 1 100.00
spi_device_csr_rw 1.140s 42.465us 1 1 100.00
spi_device_csr_aliasing 1.980s 413.807us 1 1 100.00
spi_device_same_csr_outstanding 2.690s 118.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 75.310us 1 1 100.00
spi_device_csr_rw 1.140s 42.465us 1 1 100.00
spi_device_csr_aliasing 1.980s 413.807us 1 1 100.00
spi_device_same_csr_outstanding 2.690s 118.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.540s 2553.958us 1 1 100.00
spi_device_tl_intg_err 4.940s 1155.658us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.940s 1155.658us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 38128866291869244480207636260906689258353166702416213719522466892248819372420 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 5579419 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 5579419 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1002])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 40612526212093238834853537120141117653291856488677512509472098938008666044484 76
UVM_ERROR @ 1279931 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1d7 [111010111] vs 0x0 [0])
UVM_ERROR @ 1357931 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17 [10111] vs 0x0 [0])
UVM_ERROR @ 1448931 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x269 [1001101001] vs 0x0 [0])
UVM_ERROR @ 1540931 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x13b [100111011] vs 0x0 [0])