Simulation Results: spi_host

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.41 %
  • code
  • 91.14 %
  • assert
  • 95.27 %
  • func
  • 87.82 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 103.000s 11129.039us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 9.000s 20.829us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 9.000s 51.985us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 10.000s 247.170us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 9.000s 18.404us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 9.000s 38.073us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 9.000s 51.985us 1 1 100.00
spi_host_csr_aliasing 9.000s 18.404us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 9.000s 19.601us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 9.000s 18.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 311.213us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 160.693us 1 1 100.00
spi_host_error_cmd 9.000s 20.078us 1 1 100.00
spi_host_event 12.000s 2322.995us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 378.806us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 378.806us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 378.806us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 142.000s 11509.223us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 24.000s 2028.272us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 26.451us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 378.806us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 378.806us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 103.000s 11129.039us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 103.000s 11129.039us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 9.000s 1324.945us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 342.804us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 9.000s 3059.404us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 10.000s 445.403us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 160.693us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 9.000s 213.924us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 9.000s 26.688us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 9.000s 134.273us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 9.000s 134.273us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 20.829us 1 1 100.00
spi_host_csr_rw 9.000s 51.985us 1 1 100.00
spi_host_csr_aliasing 9.000s 18.404us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 17.885us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 20.829us 1 1 100.00
spi_host_csr_rw 9.000s 51.985us 1 1 100.00
spi_host_csr_aliasing 9.000s 18.404us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 17.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 9.000s 55.769us 1 1 100.00
spi_host_sec_cm 1.000s 91.745us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 9.000s 55.769us 1 1 100.00