Simulation Results: sram_ctrl/main

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.25 %
  • code
  • 94.32 %
  • assert
  • 97.83 %
  • func
  • 90.60 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 706.506us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 39.748us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 29.271us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 42.098us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 353.710us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 29.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.566us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 276.000s 44538.965us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 103.000s 7360.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 43.000s 5369.314us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 205.000s 19242.708us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 184.000s 63209.509us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 54.000s 14988.289us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 53.000s 45818.318us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 2677.096us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 438.436us 1 1 100.00
sram_ctrl_partial_access_b2b 84.000s 15321.767us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 677.572us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 1553.602us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 1349.492us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1577.102us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1406.712us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 706.506us 1 1 100.00
sram_ctrl_partial_access 4.000s 438.436us 1 1 100.00
sram_ctrl_access_during_key_req 54.000s 14988.289us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 410.000s 55045.519us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 17.658us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 67.241us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 67.241us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 39.748us 1 1 100.00
sram_ctrl_csr_rw 2.000s 29.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.566us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 23.212us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 39.748us 1 1 100.00
sram_ctrl_csr_rw 2.000s 29.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.566us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 23.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 3986.677us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 246.764us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 246.764us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1577.102us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1577.102us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 29.271us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2677.096us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2677.096us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2677.096us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 53.000s 45818.318us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 3986.677us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 706.506us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 706.506us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 2677.096us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 53.000s 45818.318us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 706.506us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 325.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 993.304us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 83252033063695124955978311467473005453230965054883057712014327253914522533229 None
sram_ctrl_mubi_enc_err 115316370586311764334135281486431087889792118240262963448403391941483453279703 None