Simulation Results: sram_ctrl/ret

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.51 %
  • code
  • 81.46 %
  • assert
  • 97.26 %
  • func
  • 92.80 %
  • block
  • 91.78 %
  • line
  • 93.41 %
  • branch
  • 87.44 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 157.461us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 88.596us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 47.985us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 59.417us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.351us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 40.578us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 47.985us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.351us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 13.000s 722.934us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 219.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 1686.078us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 143.000s 2200.047us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 312.793us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 775.310us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 805.969us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 750.731us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 31.107us 1 1 100.00
sram_ctrl_partial_access_b2b 141.000s 14251.758us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 66.606us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 128.039us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 61.388us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1002.354us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 265.900us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 157.461us 1 1 100.00
sram_ctrl_partial_access 2.000s 31.107us 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 775.310us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 69.000s 7112.995us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 80.248us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 24.616us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 24.616us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 88.596us 1 1 100.00
sram_ctrl_csr_rw 1.000s 47.985us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.351us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.275us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 88.596us 1 1 100.00
sram_ctrl_csr_rw 1.000s 47.985us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.351us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3144.961us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 251.070us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 251.070us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1002.354us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1002.354us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 47.985us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 750.731us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 750.731us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 750.731us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 805.969us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3144.961us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 157.461us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 157.461us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 750.731us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 805.969us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 157.461us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 15.000s 819.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 591.894us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 9100004015596035561931490520036323144138011779311465119391891950637033142288 None
sram_ctrl_mubi_enc_err 103038875731296626833875219035985381749807991137901558649463041391490024585453 None