Simulation Results: sysrst_ctrl

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 82.15 %
  • code
  • 90.93 %
  • assert
  • 90.62 %
  • func
  • 64.90 %
  • line
  • 96.15 %
  • branch
  • 96.74 %
  • cond
  • 93.80 %
  • toggle
  • 100.00 %
  • FSM
  • 67.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.540s 2116.048us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.070s 2480.162us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.640s 2175.058us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.340s 2574.497us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.390s 6052.896us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 5.160s 2068.144us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 3.590s 4970.587us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.620s 2193.710us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.630s 2062.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 5.160s 2068.144us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.620s 2193.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 258.450s 159546.872us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 13.910s 32554.800us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 158.010s 229715.299us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.140s 3227.724us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.390s 2564.723us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.680s 2261.615us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.680s 3195.587us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 4.770s 2609.437us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.650s 3035.488us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 51.380s 30718.534us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 15.820s 34283.202us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.980s 2012.768us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.500s 2010.211us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.980s 2037.714us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.980s 2037.714us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.390s 6052.896us 1 1 100.00
sysrst_ctrl_csr_rw 5.160s 2068.144us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.620s 2193.710us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.340s 5151.884us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.390s 6052.896us 1 1 100.00
sysrst_ctrl_csr_rw 5.160s 2068.144us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.620s 2193.710us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.340s 5151.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 20.700s 22028.288us 1 1 100.00
sysrst_ctrl_tl_intg_err 12.370s 42680.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 12.370s 42680.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 10.430s 5386.778us 1 1 100.00