Simulation Results: uart

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.34 %
  • code
  • 92.58 %
  • assert
  • 97.98 %
  • func
  • 62.46 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.02 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.990s 593.324us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 14.140us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 23.484us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.190s 697.089us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.630s 14.655us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.760s 30.941us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 23.484us 1 1 100.00
uart_csr_aliasing 0.630s 14.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 105.170s 226142.842us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.990s 593.324us 1 1 100.00
uart_tx_rx 105.170s 226142.842us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.240s 57669.339us 1 1 100.00
uart_rx_parity_err 55.610s 49717.265us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 105.170s 226142.842us 1 1 100.00
uart_intr 10.240s 57669.339us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 100.120s 137396.161us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 63.410s 130900.673us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.160s 31277.456us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.240s 57669.339us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.240s 57669.339us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.240s 57669.339us 1 1 100.00
perf 1 1 100.00
uart_perf 219.190s 16550.174us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.790s 1472.315us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.790s 1472.315us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.010s 4180.430us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.170s 1618.192us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.080s 1076.483us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.300s 5325.781us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 194.140s 286558.293us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 603.320s 401238.695us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.640s 21.217us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.600s 23.052us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.260s 75.360us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.260s 75.360us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 14.140us 1 1 100.00
uart_csr_rw 0.640s 23.484us 1 1 100.00
uart_csr_aliasing 0.630s 14.655us 1 1 100.00
uart_same_csr_outstanding 0.790s 74.295us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 14.140us 1 1 100.00
uart_csr_rw 0.640s 23.484us 1 1 100.00
uart_csr_aliasing 0.630s 14.655us 1 1 100.00
uart_same_csr_outstanding 0.790s 74.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.800s 37.245us 1 1 100.00
uart_tl_intg_err 1.030s 83.828us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.030s 83.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 32.570s 53635.251us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 100456960758391753025987771936447995029011277072807281919281482136511618433719 80
UVM_ERROR @ 1367774580 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1368107912 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2215604522 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 2215771188 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty