Simulation Results: adc_ctrl

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.48 %
  • code
  • 96.27 %
  • assert
  • 96.60 %
  • func
  • 18.56 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 94.62 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 13.550s 5896.593us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.300s 939.596us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.330s 332.039us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 11.530s 26682.983us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.240s 437.752us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.640s 444.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.330s 332.039us 1 1 100.00
adc_ctrl_csr_aliasing 1.240s 437.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 17.240s 36845.646us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 26.220s 53549.157us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 8.870s 17669.219us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 73.690s 37208.640us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 149.180s 69125.462us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 184.960s 78751.619us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 39.150s 23577.090us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 9.200s 17839.093us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.670s 5143.510us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 12.560s 34539.812us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 215.340s 85428.017us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 20.850s 40625.710us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.120s 497.322us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.090s 322.496us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.910s 438.347us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.910s 438.347us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.300s 939.596us 1 1 100.00
adc_ctrl_csr_rw 1.330s 332.039us 1 1 100.00
adc_ctrl_csr_aliasing 1.240s 437.752us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.230s 1728.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.300s 939.596us 1 1 100.00
adc_ctrl_csr_rw 1.330s 332.039us 1 1 100.00
adc_ctrl_csr_aliasing 1.240s 437.752us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.230s 1728.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.780s 4649.659us 1 1 100.00
adc_ctrl_tl_intg_err 12.230s 4347.146us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 12.230s 4347.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 8.650s 6079.389us 1 1 100.00