Simulation Results: aes/masked

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.92 %
  • code
  • 94.05 %
  • assert
  • 98.38 %
  • func
  • 71.32 %
  • block
  • 94.02 %
  • line
  • 95.68 %
  • branch
  • 86.97 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 88.715us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 101.991us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.063us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 92.331us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 528.156us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 85.230us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 183.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 92.331us 1 1 100.00
aes_csr_aliasing 2.000s 85.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 101.991us 1 1 100.00
aes_config_error 4.000s 200.956us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 101.991us 1 1 100.00
aes_config_error 4.000s 200.956us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_b2b 10.000s 268.090us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 101.991us 1 1 100.00
aes_config_error 4.000s 200.956us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 76.263us 1 1 100.00
aes_config_error 4.000s 200.956us 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 185.334us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 38.000s 2962.779us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_sideload 4.000s 169.571us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 12.000s 654.574us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 4.000s 183.396us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 59.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 131.340us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 131.340us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.063us 1 1 100.00
aes_csr_rw 1.000s 92.331us 1 1 100.00
aes_csr_aliasing 2.000s 85.230us 1 1 100.00
aes_same_csr_outstanding 2.000s 174.632us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.063us 1 1 100.00
aes_csr_rw 1.000s 92.331us 1 1 100.00
aes_csr_aliasing 2.000s 85.230us 1 1 100.00
aes_same_csr_outstanding 2.000s 174.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 120.994us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 142.337us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 1402.526us 1 1 100.00
aes_tl_intg_err 4.000s 621.956us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 621.956us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 101.991us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
aes_core_fi 4.000s 505.631us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 200.956us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_core_fi 4.000s 505.631us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 61.890us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 77.194us 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 68.449us 1 1 100.00
aes_sideload 4.000s 169.571us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 77.194us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 77.194us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 77.194us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 77.194us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 77.194us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 68.449us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 255.576us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 255.576us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 255.576us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 255.576us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 73.385us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_ctr_fi 2.000s 56.985us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 255.576us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 255.576us 0 1 0.00
aes_control_fi 2.000s 76.353us 1 1 100.00
aes_cipher_fi 18.000s 10021.328us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 18.000s 1160.565us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 70721266144329769967109157969112140591613634389189176862914405650871486372601 6879
UVM_INFO @ 120993834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 114754980863256465747599921063127797991647514092140070221224346748660539425819 7321
UVM_INFO @ 183395972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 82121709282115558954071207751464872428169626601126893599537820227969611853744 399
UVM_INFO @ 1160564771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 82914702352869116334320146505027649294715213266260433538897129771006888659809 7652
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 104590577380798446347723654829187357015241983060414319692557811841952043245131 149
UVM_INFO @ 10021328411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---