Simulation Results: alert_handler

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.23 %
  • code
  • 91.96 %
  • assert
  • 97.32 %
  • func
  • 81.42 %
  • line
  • 99.72 %
  • branch
  • 98.44 %
  • cond
  • 91.69 %
  • toggle
  • 90.91 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.650s 120.884us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.820s 405.631us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 111.600s 6177.203us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 30.460s 418.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.300s 244.636us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.820s 405.631us 1 1 100.00
alert_handler_csr_aliasing 30.460s 418.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 18.580s 997.274us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 14.900s 1652.052us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2249.180s 52665.427us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 66.180s 9679.352us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 33.850s 478.771us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 23.360s 1468.889us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 245.430s 6517.401us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1072.370s 16659.842us 1 1 100.00
alert_handler_lpg_stub_clk 2331.670s 110947.964us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1564.650s 56525.057us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 8.490s 196.276us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.590s 41.625us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.030s 6.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.170s 69.356us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.170s 69.356us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.650s 120.884us 1 1 100.00
alert_handler_csr_rw 4.820s 405.631us 1 1 100.00
alert_handler_csr_aliasing 30.460s 418.260us 1 1 100.00
alert_handler_same_csr_outstanding 15.670s 687.677us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.650s 120.884us 1 1 100.00
alert_handler_csr_rw 4.820s 405.631us 1 1 100.00
alert_handler_csr_aliasing 30.460s 418.260us 1 1 100.00
alert_handler_same_csr_outstanding 15.670s 687.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 74.450s 4135.034us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 74.450s 4135.034us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 74.450s 4135.034us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 74.450s 4135.034us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 438.780s 17747.071us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
alert_handler_tl_intg_err 38.140s 1368.993us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 38.140s 1368.993us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 74.450s 4135.034us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 9.260s 196.430us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 66.180s 9679.352us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1072.370s 16659.842us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 66.180s 9679.352us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2249.180s 52665.427us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2249.180s 52665.427us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 14.270s 1053.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 6.170s 111.924us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 30672975762266065075536088930510636627218207810550806276807418379239668110530 129
UVM_INFO @ 6517400740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 40537662816303142185625254033795968704467654016956663804907682607987987291978 174
UVM_INFO @ 196276218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 81578701290430503664610781765884701843156543869039279905093656672006008857259 89
UVM_INFO @ 111923769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---