Simulation Results

Simulation Results: chip

31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
72.82 %

code
76.02 %

assert
96.74 %

func
45.71 %

line
93.90 %

branch
93.41 %

cond
89.12 %

toggle
70.34 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		85.17%
V2S		100.00%
V3		56.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	118.810s	2532.500us	1	1	100.00
	chip_sw_example_manufacturer	261.100s	2816.375us	1	1	100.00
	chip_sw_example_concurrency	203.740s	2272.316us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	357.420s	8950.758us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	627.240s	9338.086us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2814.310s	36080.547us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	9895.710s	77291.266us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	551.950s	10028.830us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	9895.710s	77291.266us	1	1	100.00
	chip_csr_rw	627.240s	9338.086us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.220s	54.058us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	429.560s	4012.312us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	429.560s	4012.312us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	429.560s	4012.312us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	464.470s	3796.259us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	464.470s	3796.259us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	525.200s	4092.803us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	513.470s	4360.558us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	383.090s	4177.617us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	468.410s	4155.581us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	398.590s	3505.302us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	374.590s	4257.841us	1	1	100.00

224/263 passed

85.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	477.140s	12151.059us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	477.140s	12151.059us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	332.460s	3116.865us	1	1	100.00
chip_sw_sleep_pin_wake				0	1	0.00
	chip_sw_sleep_pin_wake	242.240s	2745.509us	0	1	0.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	253.900s	3168.788us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	216.200s	3921.651us	1	1	100.00
	chip_tap_straps_testunlock0	473.880s	7562.599us	1	1	100.00
	chip_tap_straps_rma	214.700s	3055.405us	1	1	100.00
	chip_tap_straps_prod	1074.490s	13729.665us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	735.820s	5567.318us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	735.820s	5567.318us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	727.300s	6783.722us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1666.190s	11555.685us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4218.360s	19063.852us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.240s	2341.527us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	784.170s	6050.199us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	228.100s	2969.065us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1532.810s	10301.454us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	288.980s	2833.289us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	519.890s	4943.814us	1	1	100.00
	chip_sw_clkmgr_jitter	165.480s	2223.637us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	287.260s	3317.465us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	724.400s	5701.656us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	181.480s	2516.300us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	245.620s	3193.396us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	181.480s	2516.300us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	227.060s	3068.103us	1	1	100.00
	chip_sw_aon_timer_smoketest	197.530s	2545.526us	1	1	100.00
	chip_sw_clkmgr_smoketest	242.670s	2669.153us	1	1	100.00
	chip_sw_csrng_smoketest	231.500s	2513.496us	1	1	100.00
	chip_sw_entropy_src_smoketest	1127.090s	6785.188us	1	1	100.00
	chip_sw_gpio_smoketest	263.340s	2690.465us	1	1	100.00
	chip_sw_hmac_smoketest	308.300s	3547.047us	1	1	100.00
	chip_sw_kmac_smoketest	228.840s	2710.499us	1	1	100.00
	chip_sw_otbn_smoketest	1444.370s	7911.903us	1	1	100.00
	chip_sw_pwrmgr_smoketest	314.420s	4804.748us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	321.880s	4937.523us	1	1	100.00
	chip_sw_rv_plic_smoketest	208.350s	2472.726us	1	1	100.00
	chip_sw_rv_timer_smoketest	210.720s	2553.544us	1	1	100.00
	chip_sw_rstmgr_smoketest	199.180s	2757.037us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	205.920s	2917.190us	1	1	100.00
	chip_sw_uart_smoketest	232.440s	3005.232us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	192.110s	2917.674us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	477.500s	5335.172us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	20467.960s	127639.384us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3644.920s	15324.378us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	538.630s	10195.625us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	472.790s	4296.188us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	443.330s	9642.448us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.151s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	263.780s	9366.353us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	263.780s	9366.353us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	9895.710s	77291.266us	1	1	100.00
	chip_same_csr_outstanding	3491.510s	32764.251us	1	1	100.00
	chip_csr_hw_reset	357.420s	8950.758us	1	1	100.00
	chip_csr_rw	627.240s	9338.086us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	9895.710s	77291.266us	1	1	100.00
	chip_same_csr_outstanding	3491.510s	32764.251us	1	1	100.00
	chip_csr_hw_reset	357.420s	8950.758us	1	1	100.00
	chip_csr_rw	627.240s	9338.086us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	11.090s	131.956us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.700s	38.312us	1	1	100.00
	xbar_smoke_large_delays	60.250s	8680.394us	1	1	100.00
	xbar_smoke_slow_rsp	39.240s	3973.801us	1	1	100.00
	xbar_random_zero_delays	13.600s	119.422us	1	1	100.00
	xbar_random_large_delays	104.180s	14767.818us	1	1	100.00
	xbar_random_slow_rsp	177.120s	16840.287us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	14.200s	153.464us	1	1	100.00
	xbar_error_and_unmapped_addr	33.760s	1155.187us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	16.720s	208.670us	1	1	100.00
	xbar_error_and_unmapped_addr	33.760s	1155.187us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	15.510s	158.467us	1	1	100.00
	xbar_access_same_device_slow_rsp	526.280s	50854.333us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	11.360s	379.667us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	34.500s	564.687us	1	1	100.00
	xbar_stress_all_with_error	300.550s	12309.085us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	396.060s	3367.343us	1	1	100.00
	xbar_stress_all_with_reset_error	303.620s	2920.476us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3644.920s	15324.378us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3328.050s	31785.618us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3727.930s	19578.941us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2892.050s	11108.548us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3932.700s	16054.295us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3945.650s	17015.829us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3864.840s	15895.178us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3790.060s	15297.470us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2913.090s	11463.103us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3840.140s	15803.478us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3900.750s	15603.713us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3933.000s	16879.940us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3800.320s	15636.154us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5254.110s	19677.812us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	6543.780s	25374.302us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	7071.610s	24397.598us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6913.680s	25010.128us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6612.280s	23274.321us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5124.330s	23753.206us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	6570.130s	30970.207us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6835.080s	28358.377us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	7021.590s	30988.905us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6443.450s	21859.046us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3041.360s	17801.235us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3691.260s	22837.385us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3748.560s	14994.938us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	4080.190s	21397.076us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3577.120s	20992.928us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2948.550s	18057.221us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3849.300s	18647.112us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3766.610s	26480.323us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3903.810s	23165.802us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3808.270s	20662.558us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	3051.180s	11207.255us	1	1	100.00
	rom_e2e_asm_init_dev	4027.540s	15927.639us	1	1	100.00
	rom_e2e_asm_init_prod	3993.150s	15041.264us	1	1	100.00
	rom_e2e_asm_init_prod_end	4053.260s	15836.861us	1	1	100.00
	rom_e2e_asm_init_rma	3720.600s	15337.066us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7802.590s	30641.360us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7755.940s	29184.028us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7554.430s	29184.252us	1	1	100.00
rom_e2e_static_critical				0	1	0.00
	rom_e2e_static_critical	95.080s	1895.457us	0	1	0.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.185s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.185s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	262.590s	3035.259us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.240s	2341.527us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	236.200s	2808.471us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	262.180s	2847.588us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1120.600s	7372.115us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	194.280s	2478.955us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	479.670s	5541.799us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	574.970s	5513.508us	1	1	100.00
	chip_plic_all_irqs_10	368.690s	3878.462us	1	1	100.00
	chip_plic_all_irqs_20	461.270s	3989.101us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	241.100s	2510.121us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1166.900s	9679.953us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	334.700s	4310.116us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	188.570s	2710.255us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	323.420s	2835.964us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1633.000s	9763.799us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1170.350s	7585.840us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	889.460s	7965.049us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10727.980s	255411.455us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	294.240s	3756.327us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	314.420s	4804.748us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	294.240s	3756.327us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	516.050s	7260.637us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	516.050s	7260.637us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	349.370s	5888.431us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	417.440s	4918.492us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	833.640s	5992.583us	1	1	100.00
	chip_sw_aes_idle	262.180s	2847.588us	1	1	100.00
	chip_sw_hmac_enc_idle	269.290s	2840.585us	1	1	100.00
	chip_sw_kmac_idle	216.820s	2459.204us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	387.310s	4897.867us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	401.930s	3583.845us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	341.770s	3875.501us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	311.970s	4124.188us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	818.900s	10473.047us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	515.040s	3633.555us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	584.720s	4673.917us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	510.960s	3765.256us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	452.350s	4728.638us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	537.770s	3960.084us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	451.440s	4885.219us	1	1	100.00
	chip_sw_ast_clk_outputs	727.300s	6783.722us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	865.410s	11428.316us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	510.960s	3765.256us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	452.350s	4728.638us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4218.360s	19063.852us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.240s	2341.527us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	784.170s	6050.199us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	228.100s	2969.065us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1532.810s	10301.454us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	288.980s	2833.289us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	519.890s	4943.814us	1	1	100.00
	chip_sw_clkmgr_jitter	165.480s	2223.637us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	180.760s	2738.605us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4579.570s	25536.256us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	249.460s	2878.279us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	217.750s	3207.297us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1373.380s	10810.792us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	214.400s	3344.296us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	470.700s	4933.681us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	1515.760s	11178.704us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	727.300s	6783.722us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	531.690s	4437.347us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	579.160s	10597.260us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1633.000s	9763.799us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1339.600s	7612.928us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	433.310s	3960.670us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	979.090s	9317.988us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	238.680s	2751.343us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	5433.980s	24057.891us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	192.950s	2192.253us	1	1	100.00
	chip_sw_edn_entropy_reqs	907.440s	6509.600us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	192.950s	2192.253us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1339.600s	7612.928us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	186.490s	2792.115us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	234.300s	2785.933us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	228.100s	2969.065us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	269.290s	2840.585us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	2072.090s	11570.969us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2042.520s	12010.380us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	593.730s	5369.735us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	599.440s	5147.514us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	669.280s	5289.287us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	401.910s	4417.631us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1869.910s	11412.530us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1532.810s	10301.454us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1110.950s	7593.003us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1120.600s	7372.115us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.146s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	210.350s	2930.540us	1	1	100.00
	chip_sw_kmac_mode_kmac	267.010s	2967.314us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	288.980s	2833.289us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1869.910s	11412.530us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	480.660s	7870.719us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1741.170s	9929.415us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	216.820s	2459.204us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	479.670s	5541.799us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	216.200s	3921.651us	1	1	100.00
	chip_tap_straps_rma	214.700s	3055.405us	1	1	100.00
	chip_tap_straps_prod	1074.490s	13729.665us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	231.950s	2668.776us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1743.920s	11356.420us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	418.490s	10010.280us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	284.190s	3423.020us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	716.610s	5120.600us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	839.790s	7580.652us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	750.330s	5684.194us	0	1	0.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	418.890s	4309.812us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1869.910s	11412.530us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	948.850s	22968.496us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	550.130s	6668.655us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	865.410s	11428.316us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	515.040s	3633.555us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	584.720s	4673.917us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	510.960s	3765.256us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	452.350s	4728.638us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	537.770s	3960.084us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	451.440s	4885.219us	1	1	100.00
	chip_tap_straps_dev	216.200s	3921.651us	1	1	100.00
	chip_tap_straps_rma	214.700s	3055.405us	1	1	100.00
	chip_tap_straps_prod	1074.490s	13729.665us	1	1	100.00
	chip_rv_dm_lc_disabled	80.080s	3625.943us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	468.430s	6116.325us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	453.790s	6789.475us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	417.210s	7565.888us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	2211.560s	26399.051us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.173s	0.000us	0	1	0.00
	chip_rv_dm_lc_disabled	80.080s	3625.943us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1576.530s	18888.858us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1744.900s	21654.241us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1748.790s	20794.865us	1	1	100.00
	chip_sw_lc_walkthrough_rma	1041.200s	14723.121us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.173s	0.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	209.520s	3787.525us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	232.430s	5175.150us	1	1	100.00
	rom_volatile_raw_unlock	251.370s	5345.688us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4209.500s	17111.611us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4218.360s	19063.852us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	833.640s	5992.583us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	833.640s	5992.583us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	833.640s	5992.583us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	442.670s	3509.259us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	442.670s	3509.259us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1869.910s	11412.530us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	447.270s	3693.433us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.164s	0.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	442.670s	3509.259us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1869.910s	11412.530us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	447.270s	3693.433us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.164s	0.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	417.660s	5233.869us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	231.950s	2668.776us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	284.190s	3423.020us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	716.610s	5120.600us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	839.790s	7580.652us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	750.330s	5684.194us	0	1	0.00
	chip_sw_lc_ctrl_transition	2044.500s	30657.457us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1134.630s	7235.847us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	447.170s	6272.954us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	159.320s	2415.541us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	220.530s	2994.845us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	457.030s	6768.060us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	355.920s	4089.961us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1404.820s	23253.929us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1018.630s	14929.015us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	516.050s	7260.637us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	255.150s	3438.827us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	504.190s	5370.384us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	447.170s	6272.954us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	337.710s	3931.389us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	205.020s	4500.434us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	374.520s	5638.331us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	194.990s	2365.484us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	370.420s	5944.079us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	752.310s	6619.388us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1356.940s	9762.781us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1390.570s	19400.455us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	232.950s	2721.636us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	948.850s	22968.496us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	948.850s	22968.496us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1356.940s	9762.781us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	370.420s	5944.079us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	504.190s	5370.384us	1	1	100.00
	chip_sw_pwrmgr_smoketest	314.420s	4804.748us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	497.990s	4995.831us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	459.870s	4833.249us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	344.540s	4449.793us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1166.900s	9679.953us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	248.060s	2663.404us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1170.350s	7585.840us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	637.640s	4231.537us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	652.050s	4559.560us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	252.980s	2992.320us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.164s	0.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	459.870s	4833.249us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	459.870s	4833.249us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	174.230s	2289.827us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1498.290s	21703.848us	1	1	100.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	87.900s	2828.737us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	497.990s	4995.831us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	217.720s	2798.681us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	221.380s	2910.383us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	214.700s	3055.405us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	80.080s	3625.943us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	574.970s	5513.508us	1	1	100.00
	chip_plic_all_irqs_10	368.690s	3878.462us	1	1	100.00
	chip_plic_all_irqs_20	461.270s	3989.101us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	188.830s	2576.098us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	193.330s	3064.472us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3644.920s	15324.378us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	388.540s	4236.037us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	255.550s	2584.283us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	274.770s	2969.246us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	282.430s	2908.819us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	447.270s	3693.433us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	519.890s	4943.814us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	208.870s	2744.796us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	231.040s	2538.727us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	550.130s	6668.655us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
	chip_sw_data_integrity_escalation	735.820s	5567.318us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	752.310s	6619.388us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1128.820s	22027.176us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	265.580s	3214.994us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	278.720s	3535.414us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	457.320s	4359.968us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1128.820s	22027.176us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1128.820s	22027.176us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3043.990s	20121.887us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3043.990s	20121.887us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	337.790s	4982.144us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.185s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	199.490s	2442.621us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	199.950s	3171.278us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	316.210s	3692.309us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	381.830s	3922.366us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1079.080s	7943.498us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6527.540s	31196.825us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2220.460s	11678.520us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	195.010s	2695.987us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	269.520s	2947.540us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	95.840s	2463.054us	1	1	100.00

14/25 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	13196.940s	72539.917us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1343.010s	6780.325us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	85.600s	2216.767us	0	1	0.00
	rom_e2e_jtag_debug_dev	100.760s	2391.345us	0	1	0.00
	rom_e2e_jtag_debug_rma	109.040s	2347.745us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	82.110s	1914.390us	0	1	0.00
	rom_e2e_jtag_inject_dev	92.790s	1745.333us	0	1	0.00
	rom_e2e_jtag_inject_rma	102.430s	1839.506us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	153.176s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	380.680s	3204.369us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	403.000s	2820.636us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	908.230s	4231.994us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1552.930s	8638.557us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	322.360s	2300.377us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	245.390s	2953.970us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	386.970s	5350.408us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	456.110s	4747.288us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1356.940s	9762.781us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	480.660s	7870.719us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	85.600s	2216.767us	0	1	0.00
	rom_e2e_jtag_debug_dev	100.760s	2391.345us	0	1	0.00
	rom_e2e_jtag_debug_rma	109.040s	2347.745us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	226.200s	2988.443us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	491.330s	4990.897us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6244.350s	37792.444us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6244.350s	37792.444us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	211.170s	2760.197us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	464.470s	3796.259us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3658.870s	18532.330us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	51.750s	10.400us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	102.460s	1815.846us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	263.000s	2748.558us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	221.920s	3115.923us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.098s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	769.000s	10010.200us	0	1	0.00
	ate_bootstrap_one_frame	10800.149s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.142s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				15 test runs
	chip_sw_sleep_pin_wake	3169077636072588765361632910814321845516150693251387779223237290815911100159	382	UVM_INFO @ 2745.508840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_pin_retention	7382645781817707607417903422668753207004933805061346573500897164158697855968	379	UVM_INFO @ 3168.788044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	4549034804520414035749880120414416493840524439877557268259728559169556987090	374	UVM_INFO @ 2760.196662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19313675040514470454373179391783251413420598761317203540145544504164968902061	392	UVM_INFO @ 5944.079496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	81621763001080178461865000372682989423906439530939426903500589187239674605991	377	UVM_INFO @ 3438.827304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	27082522299319833528141107643026445974915776286778552203704878696646025280634	388	UVM_INFO @ 4089.961271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_lpg_sleep_mode_pings	92786921823480520450086342668564754000165407510186998629781440515559800747794	374	UVM_INFO @ 2835.964444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	98352504957325645283244703175659804181587374370982026196227379126314855437326	377	UVM_INFO @ 2744.795800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	14070922966212102545581328255337589964127644162411548029723286976681188559845	381	UVM_INFO @ 2538.727272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	96254817737335425659740487002949204742769885268314494109067009401576423469141	372	UVM_INFO @ 2516.299884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	60287916991628475474549836895186374998297999993571603709704742926350223754700	407	UVM_INFO @ 4437.346926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	53958865158252893164291367195594527550711904334135864669537553187657224712331	374	UVM_INFO @ 2994.845196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	6580036747467662816092822756542301272215795252438329358543588625200806879673	372	UVM_INFO @ 3115.922504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	113772831955725449696764933087487599529492162512296034137388464279640856752397	373	UVM_INFO @ 2415.540832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	73924158631925871317752476150577144466204015129003783701519566135471717009606	390	UVM_INFO @ 2910.382632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				7 test runs
	chip_sw_exit_test_unlocked_bootstrap	17113647057441652712801899306467563423508657578241412993369964788842466091585	None
	chip_sw_lc_walkthrough_testunlocks	52478271385954987945079864944198618821741336438756342583551227693688383662339	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10950603694168125078574681051429683106050031519660633514511746531832466148182	None
	chip_sw_keymgr_dpe_sideload_otbn	34883496572723870574523558176424165743415769086181931197107870528885493569187	None
	chip_sw_rv_core_ibex_icache_invalidate	107731093338822905535314566632901547431614485260479989516249787395065409789629	None
	ate_bootstrap_one_frame	109253200496938770848750154782810283768848613587360513779587173693582822677602	None
	ate_bootstrap_disjoint	25348887111132702203562889417366343178928942778104547443065714052918770875613	None
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	66215821960589072027716970500666258147046100038835374501467904424667796779871	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	93362321671083727260843077418266530036031930087485952927373808328535512670754	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	30881075592669965298867258473959603044938990395376836862398187379120456461115	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	102882276026020542813761105859006196720026349212910872583290886292793773322774	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	22727386962955908611742754331487936484154599888659052206366312893446726009199	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	21144870365633688736299407667599893757309595411481235355324623079743152765001	433	UVM_INFO @ 18888.857528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	42043638304839316410242511769525370567873450765289410210666267295991651220751	433	UVM_INFO @ 21654.240724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	89210159263704131042042018447843107477975071459910114675360072895606288621725	405	UVM_INFO @ 14723.121366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	113339670001107186271652609792680011463337351833011335529348306435173746546145	359	UVM_INFO @ 2216.767500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	28719519044969976106955643646474794303008348833797075157928564380897130983342	359	UVM_INFO @ 2391.345000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	8211570369337908155327107930022689863129648245180807192964511344742362528531	359	UVM_INFO @ 2347.745500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	3665036890351801651422808567583260116028621314185175845153674718915504832159	377	UVM_ERROR @ 2365.483780 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2365.483780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	101603469098331072020863059780636060459442098102769046312933780304197348701254	379	UVM_ERROR @ 4500.434442 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 4500.434442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	15747504327399718820189020962568125861595766322309897394393765469210341119268	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	109500075690884401568354522041338196587388509079808300145441474082065404114744	None	Another command (pid=597644) is running. Waiting for it to complete on the server (server_pid=204105)... Another command (pid=464686) is running. Waiting for it to complete on the server (server_pid=204105)... Another command (pid=602955) is running. Waiting for it to complete on the server (server_pid=204105)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	64223816466928544157484899744193961274986282991091115672228460247843191620378	365	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	3255944659732361040856900359255964704460653810225078643298894512444791849563	393	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	61396722986463908444012774364072634414518299753645155724296115175080871057416	342	UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	8526448791389408712277134589340497782230812959460175534600838032962466659765	404	UVM_INFO @ 5684.193500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)'				1 test run
	chip_sw_otp_ctrl_escalation	91809067557599323170879223260291488471328765480591059610546806553130641046965	380	UVM_ERROR @ 2953.969906 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError UVM_INFO @ 2953.969906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	chip_sw_lc_ctrl_test_locked0_to_scrap	110487339117501829470772771608816630864170751619692868727096961309536430236443	375	UVM_INFO @ 7565.888244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_rand_to_scrap	8808968928535339594280682619098133990875336074457193678533061822535760022686	377	UVM_INFO @ 26399.050682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	110397013230490411684369515408750674098418143129832145601484113665526261543951	371	UVM_INFO @ 2478.955206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	100125554976519264776421490343479322447987870118162575132555661141468864858571	373	UVM_INFO @ 2710.255197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				1 test run
	chip_sw_alert_handler_entropy	35172294166177071603130595901573081433695394078520941570687905779943899787074	488	UVM_INFO @ 2510.120688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	39818707509137789246338961181466153101311730883570293224963277217343719454196	428	UVM_INFO @ 12010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	59088690066950366119083546835919864438807038264845117822022936452893814805687	400	UVM_INFO @ 10597.260042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	10387168845405223425034564269043698078836083800770061444453262561640466319503	407	UVM_INFO @ 3204.368861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_mem_access	105919342437860528265037298364539977714054545089834308604771934469477581576051	5365	UVM_INFO @ 2828.737416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	28306057886945332698244996419260988943470320283054116515930637326444015022860	387	UVM_ERROR @ 2988.443400 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 2988.443400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [] vs []) RV_DM sbaddress read back check failed, got , expected				1 test run
	chip_rv_dm_lc_disabled	52143962849844375451976989423887745043849296722404747493279848558969899480256	299	UVM_INFO @ 3625.942944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	86526062819143398126847672613698950608553075411899021729735599277509492702918	391	UVM_INFO @ 11555.685388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	90283573972631884707328840961788964933749031158312784393891577638675570381030	339	UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_static_critical	104724270324558707707255783817550992615198297922087536346159459356349432755750	380	UVM_ERROR @ 1895.457117 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 1895.457117 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	rom_raw_unlock	97423894621564870081522923168610418742736277752915000960665621798428035166604	384	UVM_INFO @ 10195.624539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---