Simulation Results: clkmgr

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.04 %
  • code
  • 97.72 %
  • assert
  • 93.50 %
  • func
  • 84.91 %
  • line
  • 98.86 %
  • branch
  • 98.64 %
  • cond
  • 92.07 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.230s 33.761us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.160s 47.695us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 14.110s 1552.991us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.230s 49.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.340s 53.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
clkmgr_csr_aliasing 1.230s 49.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.960s 29.693us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.090s 215.778us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.110s 33.877us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.060s 38.919us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.230s 33.761us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 11.820s 1521.636us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.870s 146.890us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 11.820s 1521.636us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 77.580s 12992.189us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.050s 53.975us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.490s 138.422us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.490s 138.422us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.160s 47.695us 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
clkmgr_csr_aliasing 1.230s 49.117us 1 1 100.00
clkmgr_same_csr_outstanding 2.520s 199.556us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.160s 47.695us 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
clkmgr_csr_aliasing 1.230s 49.117us 1 1 100.00
clkmgr_same_csr_outstanding 2.520s 199.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.290s 25.041us 0 1 0.00
clkmgr_tl_intg_err 5.020s 825.272us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1002.130s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1002.130s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1002.130s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1002.130s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.140s 81.347us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 5.020s 825.272us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 11.820s 1521.636us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.870s 146.890us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1002.130s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.180s 30.460us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.140s 27.901us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.210s 41.444us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.420s 93.050us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.250s 62.308us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.290s 25.041us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.190s 41.714us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.290s 25.041us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.810s 694.510us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 84.200s 12834.051us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 57660341026379442434980096895466434172647134628050623377682891274905119070671 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 110939655195785487386144649566435400341194554900293140226233754027743268652137 100
UVM_INFO @ 25040777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---