Simulation Results: edn/edn0

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.75 %
  • code
  • 77.11 %
  • assert
  • 94.58 %
  • func
  • 79.56 %
  • line
  • 96.20 %
  • branch
  • 86.89 %
  • cond
  • 83.98 %
  • toggle
  • 70.61 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.340s 127.824us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.070s 18.100us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.230s 24.889us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.150s 77.414us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.470s 52.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.320s 148.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.230s 24.889us 1 1 100.00
edn_csr_aliasing 1.470s 52.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.520s 89.547us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.520s 89.547us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.520s 89.547us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.260s 41.571us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.780s 33.761us 1 1 100.00
errs 1 1 100.00
edn_err 1.410s 33.402us 1 1 100.00
disable 2 2 100.00
edn_disable 1.230s 23.131us 1 1 100.00
edn_disable_auto_req_mode 1.720s 33.466us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.540s 3578.018us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.300s 86.409us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.500s 24.797us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.340s 689.143us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.340s 689.143us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.070s 18.100us 1 1 100.00
edn_csr_rw 1.230s 24.889us 1 1 100.00
edn_csr_aliasing 1.470s 52.975us 1 1 100.00
edn_same_csr_outstanding 1.920s 157.422us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.070s 18.100us 1 1 100.00
edn_csr_rw 1.230s 24.889us 1 1 100.00
edn_csr_aliasing 1.470s 52.975us 1 1 100.00
edn_same_csr_outstanding 1.920s 157.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
edn_tl_intg_err 2.270s 179.352us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.400s 32.501us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.780s 33.761us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.780s 33.761us 1 1 100.00
edn_sec_cm 7.190s 353.297us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.780s 33.761us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.270s 179.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 109.790s 16332.231us 1 1 100.00