Simulation Results: edn/edn1

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.75 %
  • code
  • 84.45 %
  • assert
  • 97.92 %
  • func
  • 80.88 %
  • line
  • 98.41 %
  • branch
  • 93.72 %
  • cond
  • 89.46 %
  • toggle
  • 94.09 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.130s 30.405us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.200s 46.053us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.130s 33.148us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.260s 1243.662us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.260s 13.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.590s 55.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.130s 33.148us 1 1 100.00
edn_csr_aliasing 1.260s 13.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.170s 113.510us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.170s 113.510us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.170s 113.510us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.190s 21.451us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.610s 112.253us 1 1 100.00
errs 1 1 100.00
edn_err 1.350s 18.724us 1 1 100.00
disable 2 2 100.00
edn_disable 1.120s 22.320us 1 1 100.00
edn_disable_auto_req_mode 1.470s 224.037us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.630s 593.562us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.090s 38.487us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.150s 45.529us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.940s 127.953us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.940s 127.953us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.200s 46.053us 1 1 100.00
edn_csr_rw 1.130s 33.148us 1 1 100.00
edn_csr_aliasing 1.260s 13.533us 1 1 100.00
edn_same_csr_outstanding 1.430s 25.808us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.200s 46.053us 1 1 100.00
edn_csr_rw 1.130s 33.148us 1 1 100.00
edn_csr_aliasing 1.260s 13.533us 1 1 100.00
edn_same_csr_outstanding 1.430s 25.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
edn_tl_intg_err 2.250s 76.724us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.200s 41.154us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.610s 112.253us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.610s 112.253us 1 1 100.00
edn_sec_cm 5.980s 966.569us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.610s 112.253us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.250s 76.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 34.920s 1605.190us 1 1 100.00