Simulation Results: entropy_src/rng_4bits

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 76.53 %
  • code
  • 87.74 %
  • assert
  • 85.06 %
  • func
  • 56.79 %
  • block
  • 94.30 %
  • line
  • 96.96 %
  • branch
  • 86.42 %
  • toggle
  • 75.92 %
  • FSM
  • 91.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 120.128us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 30.887us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 101.308us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 8.000s 779.448us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 21.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 113.547us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 101.308us 1 1 100.00
entropy_src_csr_aliasing 2.000s 21.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 120.128us 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
entropy_src_fw_ov 265.000s 13095.827us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 265.000s 13095.827us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 496.000s 14016.692us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
entropy_src_intr 2.000s 262.695us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
entropy_src_functional_alerts 6.000s 698.004us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 100.000s 15041.654us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 56.004us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 34.913us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 218.384us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 6.000s 1866.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 6.000s 1866.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.887us 1 1 100.00
entropy_src_csr_rw 2.000s 101.308us 1 1 100.00
entropy_src_csr_aliasing 2.000s 21.927us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 135.240us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.887us 1 1 100.00
entropy_src_csr_rw 2.000s 101.308us 1 1 100.00
entropy_src_csr_aliasing 2.000s 21.927us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 135.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 88.813us 1 1 100.00
entropy_src_tl_intg_err 3.000s 233.047us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
entropy_src_cfg_regwen 2.000s 22.651us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
entropy_src_fw_ov 265.000s 13095.827us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
entropy_src_sec_cm 3.000s 88.813us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
entropy_src_sec_cm 3.000s 88.813us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 79.000s 14160.480us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
entropy_src_sec_cm 3.000s 88.813us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
entropy_src_sec_cm 3.000s 88.813us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 32.859us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 698.004us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 233.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 152.000s 14118.975us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 1.000s 33.357us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 97589688382205651534198177824512047827868519906495088299508891782970218938415 114
UVM_INFO @ 33357183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---