Simulation Results: hmac

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.89 %
  • code
  • 86.90 %
  • assert
  • 97.60 %
  • func
  • 43.16 %
  • line
  • 99.64 %
  • branch
  • 98.86 %
  • cond
  • 95.69 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.890s 547.863us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.980s 54.235us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 27.091us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.710s 1137.888us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.270s 620.820us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.810s 43.338us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 27.091us 1 1 100.00
hmac_csr_aliasing 1.270s 620.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 45.310s 26447.509us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 5.160s 422.043us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 248.970s 38534.549us 1 1 100.00
hmac_test_sha384_vectors 28.620s 1306.803us 1 1 100.00
hmac_test_sha512_vectors 373.210s 60368.206us 1 1 100.00
hmac_test_hmac256_vectors 11.240s 1546.394us 1 1 100.00
hmac_test_hmac384_vectors 15.530s 495.442us 1 1 100.00
hmac_test_hmac512_vectors 11.160s 1255.097us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 27.820s 3124.017us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 145.080s 1308.235us 1 1 100.00
error 1 1 100.00
hmac_error 128.440s 42457.454us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 137.710s 26948.175us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.890s 547.863us 1 1 100.00
hmac_long_msg 45.310s 26447.509us 1 1 100.00
hmac_back_pressure 5.160s 422.043us 1 1 100.00
hmac_datapath_stress 145.080s 1308.235us 1 1 100.00
hmac_burst_wr 27.820s 3124.017us 1 1 100.00
hmac_stress_all 761.040s 123957.865us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.890s 547.863us 1 1 100.00
hmac_long_msg 45.310s 26447.509us 1 1 100.00
hmac_back_pressure 5.160s 422.043us 1 1 100.00
hmac_datapath_stress 145.080s 1308.235us 1 1 100.00
hmac_wipe_secret 137.710s 26948.175us 1 1 100.00
hmac_test_sha256_vectors 248.970s 38534.549us 1 1 100.00
hmac_test_sha384_vectors 28.620s 1306.803us 1 1 100.00
hmac_test_sha512_vectors 373.210s 60368.206us 1 1 100.00
hmac_test_hmac256_vectors 11.240s 1546.394us 1 1 100.00
hmac_test_hmac384_vectors 15.530s 495.442us 1 1 100.00
hmac_test_hmac512_vectors 11.160s 1255.097us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.890s 547.863us 1 1 100.00
hmac_long_msg 45.310s 26447.509us 1 1 100.00
hmac_back_pressure 5.160s 422.043us 1 1 100.00
hmac_datapath_stress 145.080s 1308.235us 1 1 100.00
hmac_burst_wr 27.820s 3124.017us 1 1 100.00
hmac_error 128.440s 42457.454us 1 1 100.00
hmac_wipe_secret 137.710s 26948.175us 1 1 100.00
hmac_test_sha256_vectors 248.970s 38534.549us 1 1 100.00
hmac_test_sha384_vectors 28.620s 1306.803us 1 1 100.00
hmac_test_sha512_vectors 373.210s 60368.206us 1 1 100.00
hmac_test_hmac256_vectors 11.240s 1546.394us 1 1 100.00
hmac_test_hmac384_vectors 15.530s 495.442us 1 1 100.00
hmac_test_hmac512_vectors 11.160s 1255.097us 1 1 100.00
hmac_stress_all 761.040s 123957.865us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 761.040s 123957.865us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.780s 19.501us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.940s 17.463us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.850s 58.798us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.850s 58.798us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.980s 54.235us 1 1 100.00
hmac_csr_rw 0.790s 27.091us 1 1 100.00
hmac_csr_aliasing 1.270s 620.820us 1 1 100.00
hmac_same_csr_outstanding 2.570s 168.619us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.980s 54.235us 1 1 100.00
hmac_csr_rw 0.790s 27.091us 1 1 100.00
hmac_csr_aliasing 1.270s 620.820us 1 1 100.00
hmac_same_csr_outstanding 2.570s 168.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.140s 43.004us 1 1 100.00
hmac_tl_intg_err 3.870s 1101.836us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.870s 1101.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.890s 547.863us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.010s 438.652us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 59.490s 3277.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 6.550s 2710.740us 1 1 100.00