Simulation Results

Simulation Results: i2c

31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
85.59 %

code
78.24 %

assert
97.25 %

func
81.29 %

line
96.35 %

branch
92.19 %

cond
85.16 %

toggle
74.04 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	22.290s	6956.518us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.420s	663.286us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.920s	17.684us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.020s	87.489us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.660s	1364.079us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.020s	16.871us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	31.293us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.020s	87.489us	1	1	100.00
	i2c_csr_aliasing	1.020s	16.871us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.450s	146.623us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	1016.460s	125840.119us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	71.310s	6461.328us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.030s	92.821us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	48.140s	11474.261us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	58.950s	5031.359us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.370s	138.634us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.600s	613.430us	1	1	100.00
	i2c_host_fifo_reset_rx	9.460s	244.264us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	71.450s	13640.802us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	31.720s	1642.850us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.350s	190.443us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.140s	1957.874us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	81.100s	43292.318us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.930s	711.306us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	13.730s	735.875us	1	1	100.00
	i2c_target_intr_smoke	4.910s	1057.070us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.640s	727.029us	1	1	100.00
	i2c_target_fifo_reset_tx	1.460s	340.792us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	60.590s	24392.868us	1	1	100.00
	i2c_target_stress_rd	13.730s	735.875us	1	1	100.00
	i2c_target_intr_stress_wr	9.110s	10359.709us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.150s	1574.370us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	35.910s	3240.261us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.170s	1249.897us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.880s	437.412us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.190s	456.974us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.340s	130.585us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	71.310s	6461.328us	1	1	100.00
	i2c_host_perf_precise	46.360s	6365.495us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	31.720s	1642.850us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.710s	65.529us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.410s	2109.790us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.920s	1904.993us	1	1	100.00
	i2c_target_nack_txstretch	1.750s	700.555us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.840s	465.443us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.710s	1806.507us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.920s	20.276us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.940s	29.187us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.080s	342.773us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.080s	342.773us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.920s	17.684us	1	1	100.00
	i2c_csr_rw	1.020s	87.489us	1	1	100.00
	i2c_csr_aliasing	1.020s	16.871us	1	1	100.00
	i2c_same_csr_outstanding	1.470s	46.128us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.920s	17.684us	1	1	100.00
	i2c_csr_rw	1.020s	87.489us	1	1	100.00
	i2c_csr_aliasing	1.020s	16.871us	1	1	100.00
	i2c_same_csr_outstanding	1.470s	46.128us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.410s	49.833us	1	1	100.00
	i2c_sec_cm	1.160s	153.303us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.410s	49.833us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.210s	4464.087us	1
target_error_intr				1
	i2c_target_unexp_stop	1.260s	347.443us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	18.880s	3701.933us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	2680631233414185548254220626614691116894370693506997210948912457110854838954	96	UVM_INFO @ 4464087286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	69368032238097162099936665926605337215961102412429229650813019672474997889210	102	UVM_INFO @ 3701932786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	82385031199556237885754187955454799171189538523215388447903067951084417838958	110	UVM_INFO @ 146623175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	3030321649792770118650215794222746253555802788422809294078425442634089903209	90	UVM_INFO @ 1957874169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	93980306017469969098022041497529133039673926891470478201379123119344120060501	84	UVM_INFO @ 347442984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	79379539311840567294909644752251646509764211041829526591986722138248419097145	84	UVM_INFO @ 700554844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---