Simulation Results: keymgr_dpe/earlgrey

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.02 %
  • code
  • 82.37 %
  • assert
  • 97.67 %
  • func
  • 15.02 %
  • line
  • 97.48 %
  • branch
  • 93.58 %
  • cond
  • 85.91 %
  • toggle
  • 59.20 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 14.250s 2661.211us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.130s 386.279us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.180s 19.712us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 5.120s 448.756us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 52.226us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.200s 81.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.180s 19.712us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 52.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 1.070s 27.291us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.060s 15.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 1.910s 48.926us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 1.910s 48.926us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.130s 386.279us 1 1 100.00
keymgr_dpe_csr_rw 1.180s 19.712us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 52.226us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.370s 78.341us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.130s 386.279us 1 1 100.00
keymgr_dpe_csr_rw 1.180s 19.712us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 52.226us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.370s 78.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.540s 546.283us 1 1 100.00
keymgr_dpe_tl_intg_err 3.420s 203.725us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.510s 190.103us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.510s 190.103us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.510s 190.103us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.510s 190.103us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 2.540s 109.350us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.540s 546.283us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.540s 546.283us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 87287662199925452862801571311988822329872563807119582563716160538506917245104 83
UVM_ERROR @ 190102782 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 190102782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 68093568380823507098524918021713909655850372308749442253163824242643588137914 83
UVM_ERROR @ 109350025 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 109350025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---