Simulation Results: lc_ctrl/volatile_unlock_disabled

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.77 %
  • code
  • 83.59 %
  • assert
  • 94.13 %
  • func
  • 91.58 %
  • line
  • 97.24 %
  • branch
  • 93.61 %
  • cond
  • 79.38 %
  • toggle
  • 86.05 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.150s 90.810us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.160s 18.247us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.080s 65.661us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.140s 188.853us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 56.561us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.110s 46.898us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.080s 65.661us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 56.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.050s 60.433us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.360s 3572.731us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 33.720us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.060s 112.113us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.740s 321.280us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_prog_failure 2.060s 112.113us 1 1 100.00
lc_ctrl_errors 4.740s 321.280us 1 1 100.00
lc_ctrl_security_escalation 3.720s 907.596us 1 1 100.00
lc_ctrl_jtag_state_failure 34.960s 14385.409us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.110s 260.246us 1 1 100.00
lc_ctrl_jtag_errors 18.230s 2024.849us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.480s 552.939us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.050s 4435.118us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.110s 260.246us 1 1 100.00
lc_ctrl_jtag_errors 18.230s 2024.849us 1 1 100.00
lc_ctrl_jtag_access 12.230s 5392.613us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.880s 814.983us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.540s 190.109us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.760s 672.642us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.560s 6083.011us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.600s 145.644us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 16.587us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.360s 88.034us 1 1 100.00
lc_ctrl_jtag_alert_test 1.640s 257.712us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.900s 843.277us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.150s 86.642us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.020s 8145.330us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 124.671us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.490s 268.346us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.490s 268.346us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 18.247us 1 1 100.00
lc_ctrl_csr_rw 1.080s 65.661us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 56.561us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.360s 71.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 18.247us 1 1 100.00
lc_ctrl_csr_rw 1.080s 65.661us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 56.561us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.360s 71.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
lc_ctrl_tl_intg_err 2.300s 743.099us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.300s 743.099us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.360s 3572.731us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.660s 536.594us 1 1 100.00
lc_ctrl_sec_cm 7.370s 1280.884us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.720s 907.596us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.050s 60.433us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.050s 4435.118us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.490s 325.660us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.490s 325.660us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.250s 2257.838us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.660s 1588.564us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.660s 1588.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 23.420s 1713.404us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 78051574311102670982553682475060448648892864875403733663406069145324477511237 1212
UVM_INFO @ 1713403596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---