Simulation Results: lc_ctrl/volatile_unlock_enabled

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.68 %
  • code
  • 84.19 %
  • assert
  • 94.13 %
  • func
  • 93.73 %
  • line
  • 97.26 %
  • branch
  • 93.86 %
  • cond
  • 79.97 %
  • toggle
  • 84.43 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.280s 17.454us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.170s 17.554us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.914us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.160s 449.743us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 30.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.740s 147.513us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.050s 16.914us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 30.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.930s 683.006us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.840s 10140.962us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.130s 49.017us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.710s 62.641us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.420s 457.651us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_prog_failure 1.710s 62.641us 1 1 100.00
lc_ctrl_errors 5.420s 457.651us 1 1 100.00
lc_ctrl_security_escalation 9.220s 694.643us 1 1 100.00
lc_ctrl_jtag_state_failure 20.550s 4179.406us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.350s 1773.988us 1 1 100.00
lc_ctrl_jtag_errors 32.190s 10924.062us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.200s 66.236us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.420s 654.305us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.350s 1773.988us 1 1 100.00
lc_ctrl_jtag_errors 32.190s 10924.062us 1 1 100.00
lc_ctrl_jtag_access 8.450s 613.965us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.260s 2803.558us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.370s 47.755us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.710s 196.818us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.420s 535.720us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.710s 73.990us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.260s 110.616us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.520s 158.149us 1 1 100.00
lc_ctrl_jtag_alert_test 1.410s 33.188us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.370s 520.321us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 28.523us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 116.950s 78174.420us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 15.555us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.190s 615.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.190s 615.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 17.554us 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.914us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 30.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.360s 32.473us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 17.554us 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.914us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 30.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.360s 32.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
lc_ctrl_tl_intg_err 2.670s 117.947us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.670s 117.947us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.840s 10140.962us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 12.210s 1592.254us 1 1 100.00
lc_ctrl_sec_cm 6.230s 422.585us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.220s 694.643us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.930s 683.006us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.420s 654.305us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.360s 5621.819us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.360s 5621.819us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.420s 255.308us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.660s 546.566us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.660s 546.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 25.100s 7267.249us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 63072983624772741708394573086652350995423220869873033856164277215497590620867 4905
UVM_INFO @ 7267248611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---