Simulation Results: otbn

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.23 %
  • code
  • 86.04 %
  • assert
  • 89.76 %
  • func
  • 97.88 %
  • block
  • 99.22 %
  • line
  • 99.44 %
  • branch
  • 94.34 %
  • toggle
  • 84.17 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 14.000s 152.976us 1 1 100.00
otbn_smoke_vectorized 11.000s 22.347us 1 1 100.00
single_binary 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 18.985us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 25.808us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 10.000s 316.036us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 123.724us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 161.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 25.808us 1 1 100.00
otbn_csr_aliasing 5.000s 123.724us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 49.000s 749.944us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 18.000s 1032.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 31.000s 429.509us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 73.000s 395.878us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 35.000s 65.350us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 97.000s 833.925us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 13.000s 79.966us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 12.000s 32.939us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 54.414us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 82.013us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 44.273us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 10.000s 123.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 10.000s 123.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 18.985us 1 1 100.00
otbn_csr_rw 4.000s 25.808us 1 1 100.00
otbn_csr_aliasing 5.000s 123.724us 1 1 100.00
otbn_same_csr_outstanding 5.000s 186.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 18.985us 1 1 100.00
otbn_csr_rw 4.000s 25.808us 1 1 100.00
otbn_csr_aliasing 5.000s 123.724us 1 1 100.00
otbn_same_csr_outstanding 5.000s 186.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 13.000s 25.159us 1 1 100.00
otbn_dmem_err 9.000s 45.012us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 13.000s 220.578us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 249.379us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 55.706us 1 1 100.00
otbn_urnd_err 7.000s 31.978us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 30.939us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 177.130us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 28.933us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
otbn_tl_intg_err 30.000s 538.577us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 66.000s 386.036us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 152.976us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 45.012us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 13.000s 25.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 30.000s 538.577us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 79.966us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.159us 1 1 100.00
otbn_dmem_err 9.000s 45.012us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 32.939us 1 1 100.00
otbn_illegal_mem_acc 8.000s 30.939us 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.159us 1 1 100.00
otbn_dmem_err 9.000s 45.012us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 32.939us 1 1 100.00
otbn_illegal_mem_acc 8.000s 30.939us 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 79.966us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.159us 1 1 100.00
otbn_dmem_err 9.000s 45.012us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 32.939us 1 1 100.00
otbn_illegal_mem_acc 8.000s 30.939us 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 19.000s 68.081us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 18.672us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 71.000s 198.470us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 71.000s 198.470us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 14.000s 230.122us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 431.604us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 190.568us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 190.568us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 16.540us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 35.000s 65.350us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 31.040us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 12.000s 185.477us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 731.000s 3294.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 284.000s 1256.518us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 104623432883106593181735178735479209297344009881029621539891623246102957093579 186
UVM_INFO @ 1256518431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---