Simulation Results: otp_ctrl

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 82.94 %
  • code
  • 78.26 %
  • assert
  • 94.19 %
  • func
  • 76.36 %
  • line
  • 88.52 %
  • branch
  • 83.51 %
  • cond
  • 90.52 %
  • toggle
  • 82.92 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.130s 784.233us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.870s 94.592us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.960s 157.303us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.980s 167.624us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.240s 117.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.590s 75.150us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.960s 157.303us 1 1 100.00
otp_ctrl_csr_aliasing 2.240s 117.471us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.850s 42.154us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.390s 60.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 19.230s 3758.330us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.110s 386.893us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 7.600s 429.272us 1 1 100.00
otp_ctrl_check_fail 11.160s 656.485us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.670s 733.831us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 16.380s 1452.626us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 15.490s 826.162us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 19.950s 1910.214us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.340s 204.949us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 18.480s 2138.598us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 179.390s 65858.715us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.910s 154.039us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.690s 172.114us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 6.500s 1405.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 6.500s 1405.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 94.592us 1 1 100.00
otp_ctrl_csr_rw 1.960s 157.303us 1 1 100.00
otp_ctrl_csr_aliasing 2.240s 117.471us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.740s 77.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 94.592us 1 1 100.00
otp_ctrl_csr_rw 1.960s 157.303us 1 1 100.00
otp_ctrl_csr_aliasing 2.240s 117.471us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.740s 77.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
otp_ctrl_tl_intg_err 13.530s 1479.113us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.530s 1479.113us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_macro_errs 2.340s 204.949us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_macro_errs 2.340s 204.949us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.740s 56.068us 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.110s 386.893us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 11.160s 656.485us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 18.950s 2882.815us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 155.230s 37921.784us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.670s 733.831us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.080s 275.964us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.340s 204.949us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.460s 8456.287us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 31.750s 4477.943us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 94632066832822847199869142939849290484899728126275687281441117856319732719946 355
UVM_INFO @ 204949051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 47575008867476525416831343534299634462080759540538252406225591847918716860822 5673
UVM_INFO @ 4477943049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---