Simulation Results: pwrmgr

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 94.50 %
  • assert
  • 97.91 %
  • func
  • 95.06 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 93.92 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.900s 32.038us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.910s 203.291us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.040s 1711.499us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 23.894us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.100s 118.965us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 23.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.930s 76.616us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.930s 76.616us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.980s 29.758us 1 1 100.00
pwrmgr_lowpower_invalid 0.930s 52.974us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.750s 35.881us 1 1 100.00
pwrmgr_reset_invalid 1.170s 97.775us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.750s 35.881us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 247.647us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 29.962us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.920s 119.044us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.270s 538.472us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.840s 28.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.810s 1237.810us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.810s 1237.810us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
pwrmgr_csr_hw_reset 0.910s 203.291us 1 1 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 23.894us 1 1 100.00
pwrmgr_same_csr_outstanding 3600.030s 0.000us 0 1 0.00
tl_d_partial_access 3 4 75.00
pwrmgr_csr_hw_reset 0.910s 203.291us 1 1 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 23.894us 1 1 100.00
pwrmgr_same_csr_outstanding 3600.030s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.029s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.029s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.330s 1325.117us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.730s 247.647us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.430s 1317.178us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.090s 72.839us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 30.582us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.890s 49.074us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.024s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.950s 350.519us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.750s 18.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 1.080s 193.619us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.026s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
pwrmgr_glitch 16168506900523989509160349319524524610119802929127888737200609074025564707787 None
pwrmgr_tl_intg_err 10027210588247411800161382770650163408167986227411461459717141437779980745506 None
pwrmgr_sec_cm 28231359277330271652769152476490394279486740864157404575041561116029556725945 None
pwrmgr_stress_all_with_rand_reset 100831343927515944991327381007475571175426107176286334218031010584392338872514 None
pwrmgr_same_csr_outstanding 79965969873428582248925375354271789620907668704410531349287503555368553366026 None