Simulation Results: rom_ctrl/192kb

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 92.66 %
  • assert
  • 97.39 %
  • func
  • 96.64 %
  • line
  • 98.82 %
  • branch
  • 98.19 %
  • cond
  • 98.22 %
  • toggle
  • 94.76 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 18.730s 2063.064us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 21.970s 53.844us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.270s 76.431us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.480s 258.982us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 12.340s 54.129us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.790s 78.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.270s 76.431us 1 1 100.00
rom_ctrl_csr_aliasing 12.340s 54.129us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 11.590s 54.297us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 12.420s 50.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 18.410s 4097.234us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 75.430s 97.616us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 22.890s 74.591us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 10.890s 60.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 13.720s 176.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 13.720s 176.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 21.970s 53.844us 1 1 100.00
rom_ctrl_csr_rw 10.270s 76.431us 1 1 100.00
rom_ctrl_csr_aliasing 12.340s 54.129us 1 1 100.00
rom_ctrl_same_csr_outstanding 22.200s 314.279us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 21.970s 53.844us 1 1 100.00
rom_ctrl_csr_rw 10.270s 76.431us 1 1 100.00
rom_ctrl_csr_aliasing 12.340s 54.129us 1 1 100.00
rom_ctrl_same_csr_outstanding 22.200s 314.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 56.700s 208.342us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
rom_ctrl_tl_intg_err 192.220s 324.764us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 18.730s 2063.064us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 18.730s 2063.064us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 18.730s 2063.064us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 192.220s 324.764us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
rom_ctrl_kmac_err_chk 22.890s 74.591us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 315.940s 29323.860us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 56.700s 208.342us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 1681.530s 738.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 202.270s 22611.138us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 35284493870572935226139153005110467921427874428031653664311608393570035271934 85
UVM_INFO @ 4097233740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---