Simulation Results: rstmgr

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.55 %
  • code
  • 99.34 %
  • assert
  • 98.53 %
  • func
  • 94.78 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.400s 272.609us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.170s 155.746us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 8.140s 2471.671us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.180s 101.191us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.270s 110.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00
rstmgr_csr_aliasing 1.180s 101.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.220s 172.192us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.830s 179.156us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.260s 285.947us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.530s 1296.000us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.530s 1296.000us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.530s 1296.000us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.530s 1296.000us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 7.520s 2454.923us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.780s 81.731us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.230s 106.523us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.230s 106.523us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.170s 155.746us 1 1 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00
rstmgr_csr_aliasing 1.180s 101.191us 1 1 100.00
rstmgr_same_csr_outstanding 1.110s 139.949us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.170s 155.746us 1 1 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00
rstmgr_csr_aliasing 1.180s 101.191us 1 1 100.00
rstmgr_same_csr_outstanding 1.110s 139.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.910s 8504.974us 1 1 100.00
rstmgr_tl_intg_err 2.500s 937.032us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.910s 8504.974us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.910s 8504.974us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.500s 937.032us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.360s 204.079us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.380s 2579.053us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.460s 302.071us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.910s 8504.974us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 90.494us 1 1 100.00