Simulation Results: rv_timer

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.51 %
  • code
  • 94.36 %
  • assert
  • 98.41 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 77.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.280s 971.802us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 20.375us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.620s 13.066us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.270s 207.420us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.630s 15.404us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.700s 19.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.620s 13.066us 1 1 100.00
rv_timer_csr_aliasing 0.630s 15.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.680s 170.998us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.920s 1351.149us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 73.220s 71493.490us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 73.220s 71493.490us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.800s 3748.880us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.720s 18.390us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 15.253us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.080s 74.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.080s 74.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 20.375us 1 1 100.00
rv_timer_csr_rw 0.620s 13.066us 1 1 100.00
rv_timer_csr_aliasing 0.630s 15.404us 1 1 100.00
rv_timer_same_csr_outstanding 0.610s 21.809us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 20.375us 1 1 100.00
rv_timer_csr_rw 0.620s 13.066us 1 1 100.00
rv_timer_csr_aliasing 0.630s 15.404us 1 1 100.00
rv_timer_same_csr_outstanding 0.610s 21.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.840s 192.845us 1 1 100.00
rv_timer_tl_intg_err 1.120s 233.191us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.120s 233.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.700s 566.209us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.660s 175.545us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 33.100s 23277.450us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 47392989738687070350581456236070247080407819314601771385064155524544272258565 81
UVM_INFO @ 566208508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 6908783081265854054177331662984959826800522820313183983699436827759666576592 82
UVM_INFO @ 175544844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---