Simulation Results: spi_device/1r1w

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.18 %
  • code
  • 91.38 %
  • assert
  • 95.27 %
  • func
  • 71.88 %
  • line
  • 98.89 %
  • branch
  • 98.22 %
  • cond
  • 96.12 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 91.060s 29865.778us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.140s 40.795us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.960s 194.327us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.010s 281.178us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.150s 87.212us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.910s 1387.205us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.960s 194.327us 1 1 100.00
spi_device_csr_aliasing 1.150s 87.212us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 17.935us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.630s 69.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 44.566us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.680s 8.536us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.710s 3.672us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.170s 19.170us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.170s 19.170us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.810s 30055.245us 1 1 100.00
spi_device_tpm_sts_read 0.980s 93.536us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.730s 4161.496us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.250s 1842.464us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.160s 300.572us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.160s 300.572us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.660s 150.436us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.660s 150.436us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.660s 150.436us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.660s 150.436us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.660s 150.436us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 10.350s 5218.358us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 34.680s 6955.033us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 34.680s 6955.033us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 34.680s 6955.033us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 1.910s 182.037us 1 1 100.00
spi_device_read_buffer_direct 5.880s 4324.219us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 34.680s 6955.033us 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 88.980s 87943.268us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.790s 2693.645us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.790s 2693.645us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 8.570s 1807.450us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 91.060s 29865.778us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 121.750s 14886.786us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 237.710s 48702.644us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 44.332us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 20.923us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.540s 488.418us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.540s 488.418us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.140s 40.795us 1 1 100.00
spi_device_csr_rw 1.960s 194.327us 1 1 100.00
spi_device_csr_aliasing 1.150s 87.212us 1 1 100.00
spi_device_same_csr_outstanding 3.100s 755.257us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.140s 40.795us 1 1 100.00
spi_device_csr_rw 1.960s 194.327us 1 1 100.00
spi_device_csr_aliasing 1.150s 87.212us 1 1 100.00
spi_device_same_csr_outstanding 3.100s 755.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.400s 951.875us 1 1 100.00
spi_device_tl_intg_err 5.170s 320.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.170s 320.349us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 18693629600044440626157988560297579919115595987159757420308111433625982988163 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 6893348 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 6893348 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 22374035964942021633914821364694131569331036561592528116262478877386197103385 76
UVM_ERROR @ 930898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x30d [1100001101] vs 0x0 [0])
UVM_ERROR @ 932898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ff [1011111111] vs 0x0 [0])
UVM_ERROR @ 1012898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1f1 [111110001] vs 0x0 [0])
UVM_ERROR @ 1080898 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d5 [1111010101] vs 0x0 [0])