Simulation Results: spi_host

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.46 %
  • code
  • 91.25 %
  • assert
  • 94.90 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 72.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 28.000s 12540.014us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 8.000s 27.917us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 9.000s 20.877us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 9.000s 47.002us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 9.000s 54.144us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 9.000s 29.873us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 9.000s 20.877us 1 1 100.00
spi_host_csr_aliasing 9.000s 54.144us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 8.000s 96.040us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 9.000s 22.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 67.884us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 59.609us 1 1 100.00
spi_host_error_cmd 8.000s 181.544us 1 1 100.00
spi_host_event 427.000s 18890.038us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 84.101us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 84.101us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 84.101us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 90.000s 3319.967us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 324.096us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 47.375us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 84.101us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 84.101us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 28.000s 12540.014us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 28.000s 12540.014us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 44.822us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 1477.102us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 33.000s 8379.621us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 48.875us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 59.609us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 9.000s 95.671us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 8.000s 39.588us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 9.000s 127.889us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 9.000s 127.889us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 8.000s 27.917us 1 1 100.00
spi_host_csr_rw 9.000s 20.877us 1 1 100.00
spi_host_csr_aliasing 9.000s 54.144us 1 1 100.00
spi_host_same_csr_outstanding 8.000s 31.311us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 8.000s 27.917us 1 1 100.00
spi_host_csr_rw 9.000s 20.877us 1 1 100.00
spi_host_csr_aliasing 9.000s 54.144us 1 1 100.00
spi_host_same_csr_outstanding 8.000s 31.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 9.000s 299.395us 1 1 100.00
spi_host_sec_cm 1.000s 44.770us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 9.000s 299.395us 1 1 100.00