Simulation Results: sram_ctrl/main

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.48 %
  • code
  • 94.15 %
  • assert
  • 97.28 %
  • func
  • 95.00 %
  • block
  • 93.33 %
  • line
  • 94.31 %
  • branch
  • 90.58 %
  • toggle
  • 91.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 782.351us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 35.716us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 90.068us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 326.189us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.878us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1474.069us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 90.068us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.878us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 250.000s 8954.369us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 127.000s 2579.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 2745.671us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 102.000s 48221.803us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 210.000s 15645.116us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 49.000s 116690.143us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 46.000s 48373.934us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 29.000s 40351.625us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 4850.391us 1 1 100.00
sram_ctrl_partial_access_b2b 285.000s 73891.332us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 675.630us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 1318.459us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2465.498us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1264.182us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1676.611us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 782.351us 1 1 100.00
sram_ctrl_partial_access 5.000s 4850.391us 1 1 100.00
sram_ctrl_access_during_key_req 49.000s 116690.143us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 226.000s 55472.574us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 50.424us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 92.236us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 92.236us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 35.716us 1 1 100.00
sram_ctrl_csr_rw 1.000s 90.068us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.878us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.286us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 35.716us 1 1 100.00
sram_ctrl_csr_rw 1.000s 90.068us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.878us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 3904.279us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 366.683us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 366.683us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1264.182us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1264.182us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 90.068us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 29.000s 40351.625us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 40351.625us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 40351.625us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 46.000s 48373.934us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 3904.279us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 782.351us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 782.351us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 29.000s 40351.625us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 46.000s 48373.934us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 782.351us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 6.000s 819.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 440.060us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 79561763247887701447546075322864604775736689194475346779172717405221994336231 None
sram_ctrl_mubi_enc_err 110015263716608176884290650840903889070216476565671339110989347383506864633668 None