Simulation Results: sram_ctrl/ret

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.90 %
  • code
  • 81.35 %
  • assert
  • 97.95 %
  • func
  • 93.40 %
  • block
  • 91.78 %
  • line
  • 93.41 %
  • branch
  • 87.44 %
  • toggle
  • 77.89 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 34.354us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 28.758us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 42.315us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 132.624us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.118us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 185.383us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 42.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.118us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 376.500us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.000s 190.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 628.928us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 180.000s 3286.812us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 1940.286us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 356.983us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 548.550us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1214.878us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 54.146us 1 1 100.00
sram_ctrl_partial_access_b2b 155.000s 6009.940us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 34.794us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 35.237us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 288.948us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 755.976us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 25.956us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 34.354us 1 1 100.00
sram_ctrl_partial_access 2.000s 54.146us 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 356.983us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 13.000s 304.099us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.376us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 74.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 74.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.758us 1 1 100.00
sram_ctrl_csr_rw 2.000s 42.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.118us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 33.726us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.758us 1 1 100.00
sram_ctrl_csr_rw 2.000s 42.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.118us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 33.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 620.218us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 262.504us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 262.504us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 755.976us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 755.976us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 42.315us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1214.878us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1214.878us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1214.878us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 548.550us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.179s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 620.218us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.159s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 34.354us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 34.354us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1214.878us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 548.550us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 34.354us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 755.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 34.000s 1157.428us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 5651279244423407501512526859243134778249812411615598764241664514790672445663 None
sram_ctrl_mubi_enc_err 64597292615123889265409545320420154460631657928685235742312171508455522287821 None