Simulation Results: sysrst_ctrl

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.67 %
  • code
  • 94.40 %
  • assert
  • 96.40 %
  • func
  • 63.21 %
  • line
  • 98.21 %
  • branch
  • 98.11 %
  • cond
  • 95.56 %
  • toggle
  • 100.00 %
  • FSM
  • 80.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.000s 2133.340us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.730s 2451.783us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.590s 2437.060us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.790s 2367.832us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.350s 4021.295us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.630s 2058.981us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 24.510s 39127.570us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 1.670s 2281.274us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.650s 2048.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.630s 2058.981us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.670s 2281.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 91.480s 171171.198us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 46.220s 107308.852us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.740s 3687.622us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.920s 3343.675us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.720s 2512.916us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 3.830s 2231.014us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.260s 2775.907us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.450s 2648.295us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.470s 11659.885us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 65.630s 35301.211us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 27.050s 14253.511us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.200s 2059.841us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.460s 2029.317us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.850s 2265.638us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.850s 2265.638us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.350s 4021.295us 1 1 100.00
sysrst_ctrl_csr_rw 3.630s 2058.981us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.670s 2281.274us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.440s 5453.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.350s 4021.295us 1 1 100.00
sysrst_ctrl_csr_rw 3.630s 2058.981us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.670s 2281.274us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.440s 5453.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 37.970s 42033.960us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.750s 22259.400us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.750s 22259.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.240s 5772.348us 1 1 100.00