Simulation Results: uart

 
31/08/2026 15:30:34 DVSim: v1.52.0 sha: 6fb6d8a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.97 %
  • code
  • 91.35 %
  • assert
  • 98.27 %
  • func
  • 56.29 %
  • line
  • 99.06 %
  • branch
  • 96.97 %
  • cond
  • 94.87 %
  • toggle
  • 74.49 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.910s 953.981us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 39.319us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 24.920us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.680s 162.377us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 15.814us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.700s 56.883us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 24.920us 1 1 100.00
uart_csr_aliasing 0.720s 15.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.900s 50235.305us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.910s 953.981us 1 1 100.00
uart_tx_rx 9.900s 50235.305us 1 1 100.00
parity_error 2 2 100.00
uart_intr 19.820s 71252.072us 1 1 100.00
uart_rx_parity_err 29.440s 138928.923us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.900s 50235.305us 1 1 100.00
uart_intr 19.820s 71252.072us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 57.340s 61942.231us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 8.390s 39278.382us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 26.400s 82560.774us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 19.820s 71252.072us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 19.820s 71252.072us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 19.820s 71252.072us 1 1 100.00
perf 1 1 100.00
uart_perf 22.910s 3690.022us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.870s 1017.882us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.870s 1017.882us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 62.000s 59119.783us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.690s 5437.001us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.200s 1573.979us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 5.850s 1803.533us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 249.270s 96935.585us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 150.670s 738321.734us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.590s 66.327us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.640s 47.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.270s 91.670us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.270s 91.670us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 39.319us 1 1 100.00
uart_csr_rw 0.590s 24.920us 1 1 100.00
uart_csr_aliasing 0.720s 15.814us 1 1 100.00
uart_same_csr_outstanding 0.900s 18.645us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 39.319us 1 1 100.00
uart_csr_rw 0.590s 24.920us 1 1 100.00
uart_csr_aliasing 0.720s 15.814us 1 1 100.00
uart_same_csr_outstanding 0.900s 18.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.110s 286.621us 1 1 100.00
uart_tl_intg_err 1.060s 601.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.060s 601.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 13.820s 731.769us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 15666345947547240327331226744451158622715990920308549759880051856911649746178 84
UVM_ERROR @ 54102062674 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 55625299896 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 55625299896 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 57049498555 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr 1 test run
uart_stress_all_with_rand_reset 48737545067963959216146882485466587267705552291477773714021546856107944029632 109
UVM_ERROR @ 516418043 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 539262524 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 539262524 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_INFO @ 554408842 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/91