Simulation Results: adc_ctrl

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.71 %
  • code
  • 96.80 %
  • assert
  • 96.76 %
  • func
  • 18.56 %
  • line
  • 99.02 %
  • branch
  • 98.39 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.610s 5967.805us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.570s 931.585us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.110s 386.186us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 19.080s 28324.260us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.140s 431.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.810s 595.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.110s 386.186us 1 1 100.00
adc_ctrl_csr_aliasing 1.140s 431.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 25.630s 56372.412us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 8.050s 17806.719us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 51.690s 52210.549us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 7.340s 18201.449us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 46.600s 50606.535us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 29.850s 28332.014us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 135.050s 66297.681us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 75.060s 64386.168us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.820s 4037.935us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 51.180s 28272.927us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 194.060s 97927.874us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 26.620s 25877.747us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.570s 431.981us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.190s 344.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.440s 517.492us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.440s 517.492us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.570s 931.585us 1 1 100.00
adc_ctrl_csr_rw 1.110s 386.186us 1 1 100.00
adc_ctrl_csr_aliasing 1.140s 431.544us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.570s 4689.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.570s 931.585us 1 1 100.00
adc_ctrl_csr_rw 1.110s 386.186us 1 1 100.00
adc_ctrl_csr_aliasing 1.140s 431.544us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.570s 4689.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 8.720s 4250.832us 1 1 100.00
adc_ctrl_tl_intg_err 11.750s 5005.367us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 11.750s 5005.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.900s 3483.342us 1 1 100.00