Simulation Results: aes/masked

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.52 %
  • code
  • 93.53 %
  • assert
  • 98.23 %
  • func
  • 73.80 %
  • block
  • 94.17 %
  • line
  • 95.84 %
  • branch
  • 86.97 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 82.260us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 98.883us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 65.407us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 79.624us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 470.783us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 155.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 68.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 79.624us 1 1 100.00
aes_csr_aliasing 2.000s 155.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 98.883us 1 1 100.00
aes_config_error 3.000s 135.590us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 98.883us 1 1 100.00
aes_config_error 3.000s 135.590us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_b2b 17.000s 953.912us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 98.883us 1 1 100.00
aes_config_error 3.000s 135.590us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 97.546us 1 1 100.00
aes_config_error 3.000s 135.590us 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 153.428us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 13.000s 1201.123us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_sideload 3.000s 98.190us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 76.579us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 3.000s 98.006us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 222.688us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 120.833us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 120.833us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.407us 1 1 100.00
aes_csr_rw 2.000s 79.624us 1 1 100.00
aes_csr_aliasing 2.000s 155.586us 1 1 100.00
aes_same_csr_outstanding 2.000s 199.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.407us 1 1 100.00
aes_csr_rw 2.000s 79.624us 1 1 100.00
aes_csr_aliasing 2.000s 155.586us 1 1 100.00
aes_same_csr_outstanding 2.000s 199.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 151.576us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 283.944us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 2390.562us 1 1 100.00
aes_tl_intg_err 3.000s 311.687us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 311.687us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 98.883us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
aes_core_fi 3.000s 96.771us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 135.590us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_core_fi 3.000s 96.771us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 71.157us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 72.220us 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 138.335us 1 1 100.00
aes_sideload 3.000s 98.190us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.220us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.220us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 72.220us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 72.220us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 72.220us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 138.335us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 7.000s 228.018us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 7.000s 228.018us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 7.000s 228.018us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 7.000s 228.018us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 108.460us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_ctr_fi 3.000s 61.010us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 7.000s 228.018us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 7.000s 228.018us 0 1 0.00
aes_control_fi 2.000s 70.472us 1 1 100.00
aes_cipher_fi 2.000s 55.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 1173.847us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 81360439414376482955158047138323003909173219348907050136686367869528927904554 22294
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 105002520318058583718147065230328211795733546634438941981616724893747177127574 4832
UVM_INFO @ 98006272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 80387828490782491128350197030365874485799558197544507350768558248440651837721 181
UVM_INFO @ 1173847360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---