Simulation Results: aes/unmasked

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 89.62 %
  • assert
  • 97.73 %
  • func
  • 73.80 %
  • block
  • 89.33 %
  • line
  • 91.75 %
  • branch
  • 79.87 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 64.405us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 72.595us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 91.869us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 212.310us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 260.318us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 66.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 190.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 212.310us 1 1 100.00
aes_csr_aliasing 2.000s 66.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 72.595us 1 1 100.00
aes_config_error 3.000s 364.857us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 72.595us 1 1 100.00
aes_config_error 3.000s 364.857us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_b2b 8.000s 156.434us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 72.595us 1 1 100.00
aes_config_error 3.000s 364.857us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 100.614us 1 1 100.00
aes_config_error 3.000s 364.857us 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 344.134us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 136.289us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_sideload 2.000s 117.779us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 91.896us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 7.000s 397.150us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 57.579us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 62.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 62.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 91.869us 1 1 100.00
aes_csr_rw 2.000s 212.310us 1 1 100.00
aes_csr_aliasing 2.000s 66.462us 1 1 100.00
aes_same_csr_outstanding 2.000s 225.582us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 91.869us 1 1 100.00
aes_csr_rw 2.000s 212.310us 1 1 100.00
aes_csr_aliasing 2.000s 66.462us 1 1 100.00
aes_same_csr_outstanding 2.000s 225.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 7.440us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
shadow_reg_update_error 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 274.897us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 551.898us 1 1 100.00
aes_tl_intg_err 2.000s 130.309us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 130.309us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
sec_cm_main_config_shadow 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
sec_cm_gcm_config_shadow 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 72.595us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
aes_core_fi 2.000s 88.266us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 364.857us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_core_fi 2.000s 88.266us 1 1 100.00
sec_cm_aux_config_shadow 0 1 0.00
aes_shadow_reg_errors 1.000s 15.230us 0 1 0.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 70.254us 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 318.428us 1 1 100.00
aes_sideload 2.000s 117.779us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.254us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.254us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 70.254us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 70.254us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 70.254us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 318.428us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.669us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.669us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.669us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.669us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 154.359us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_ctr_fi 2.000s 98.756us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 149.669us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 149.669us 0 1 0.00
aes_control_fi 2.000s 87.831us 1 1 100.00
aes_cipher_fi 1.000s 56.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 190.182us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 78773784151781261199782024327446916741539187600285292820988391322302500045125 1415
UVM_INFO @ 7439547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 56735485660514877660119739909477960052827289829979201768963782915820687999473 20025
UVM_INFO @ 397149746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 99400441646609807295582551898746592914344191161792986767924286519022974149106 140
UVM_INFO @ 190181696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 53249384766444409080225600135750294299467858842442957462661996975432964420686 5185
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 86900991580051969870157760806216396041548616583840709270552200374619004704541 106
UVM_INFO @ 15229941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---