Simulation Results: alert_handler

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.38 %
  • code
  • 92.16 %
  • assert
  • 98.24 %
  • func
  • 83.74 %
  • line
  • 99.70 %
  • branch
  • 98.99 %
  • cond
  • 92.67 %
  • toggle
  • 92.04 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 9.110s 479.438us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.730s 250.813us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 476.420s 186115.836us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 14.260s 219.261us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.700s 116.647us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.730s 250.813us 1 1 100.00
alert_handler_csr_aliasing 14.260s 219.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 7.750s 581.040us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 27.480s 1838.950us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1862.010s 175410.378us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 20.370s 2171.580us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 8.520s 293.025us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 55.420s 1478.849us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 252.760s 7288.270us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1827.770s 48171.344us 1 1 100.00
alert_handler_lpg_stub_clk 2232.810s 167317.296us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 3537.600s 312054.566us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.190s 487.461us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.660s 182.648us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.140s 9.833us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.310s 43.513us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.310s 43.513us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 9.110s 479.438us 1 1 100.00
alert_handler_csr_rw 7.730s 250.813us 1 1 100.00
alert_handler_csr_aliasing 14.260s 219.261us 1 1 100.00
alert_handler_same_csr_outstanding 14.980s 180.478us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 9.110s 479.438us 1 1 100.00
alert_handler_csr_rw 7.730s 250.813us 1 1 100.00
alert_handler_csr_aliasing 14.260s 219.261us 1 1 100.00
alert_handler_same_csr_outstanding 14.980s 180.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 279.980s 5789.729us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 279.980s 5789.729us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 279.980s 5789.729us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 279.980s 5789.729us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 419.680s 6012.858us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
alert_handler_tl_intg_err 83.730s 2533.629us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 83.730s 2533.629us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 279.980s 5789.729us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 58.200s 5312.584us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.370s 2171.580us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1827.770s 48171.344us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.370s 2171.580us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1862.010s 175410.378us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1862.010s 175410.378us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 39.460s 1085.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 72.070s 1294.921us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 8164493507721469896851505807120397439430923746668506426245879900018162926472 155
UVM_INFO @ 7288270137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 9694327684805942022154178661283667092313441763001283388962495662147786558554 212
UVM_INFO @ 487460923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 92995754857591903122175242140875913318999268276699822525697696155022847488154 129
UVM_INFO @ 1294921198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---