Simulation Results

Simulation Results: chip

01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
67.51 %

code
71.85 %

assert
95.53 %

func
35.15 %

line
89.48 %

branch
91.80 %

cond
84.97 %

toggle
59.69 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		84.03%
V2S		100.00%
V3		60.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	120.770s	2528.195us	1	1	100.00
	chip_sw_example_manufacturer	198.620s	2539.170us	1	1	100.00
	chip_sw_example_concurrency	186.520s	2662.594us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	533.900s	10822.716us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	435.840s	7299.444us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	3062.020s	37391.671us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	7745.730s	70744.441us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	940.940s	13601.271us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	7745.730s	70744.441us	1	1	100.00
	chip_csr_rw	435.840s	7299.444us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	9.880s	212.944us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	341.400s	4634.784us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	341.400s	4634.784us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	341.400s	4634.784us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	502.340s	4550.530us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	502.340s	4550.530us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	409.360s	4266.410us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	433.880s	4415.215us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	482.700s	4715.351us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	406.600s	3546.279us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	495.860s	3727.370us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	766.760s	8520.631us	1	1	100.00

221/263 passed

84.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				0	1	0.00
	chip_padctrl_attributes	56.780s	2401.104us	0	1	0.00
chip_padctrl_attributes				0	1	0.00
	chip_padctrl_attributes	56.780s	2401.104us	0	1	0.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	275.580s	2650.459us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	486.100s	6264.341us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	220.160s	3018.590us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	1010.930s	12702.144us	1	1	100.00
	chip_tap_straps_testunlock0	410.670s	5086.654us	1	1	100.00
	chip_tap_straps_rma	180.930s	3095.854us	1	1	100.00
	chip_tap_straps_prod	144.470s	2556.372us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	550.230s	4933.505us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	550.230s	4933.505us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	711.530s	7548.861us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1210.020s	11378.490us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4021.440s	19303.196us	1	1	100.00
	chip_sw_aes_enc_jitter_en	208.720s	2294.959us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	787.810s	6509.683us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	210.000s	3023.493us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1759.260s	11590.168us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	268.210s	3178.854us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	481.740s	4850.707us	1	1	100.00
	chip_sw_clkmgr_jitter	213.810s	2620.688us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	239.140s	3323.895us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	410.160s	3672.364us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	181.470s	2912.104us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	253.050s	2584.473us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	181.470s	2912.104us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	248.770s	2473.921us	1	1	100.00
	chip_sw_aon_timer_smoketest	267.460s	2852.721us	1	1	100.00
	chip_sw_clkmgr_smoketest	212.250s	2645.354us	1	1	100.00
	chip_sw_csrng_smoketest	255.030s	2340.304us	1	1	100.00
	chip_sw_entropy_src_smoketest	804.660s	5747.313us	1	1	100.00
	chip_sw_gpio_smoketest	262.950s	2574.341us	1	1	100.00
	chip_sw_hmac_smoketest	326.920s	2676.541us	1	1	100.00
	chip_sw_kmac_smoketest	211.120s	3006.151us	1	1	100.00
	chip_sw_otbn_smoketest	1122.190s	6840.249us	1	1	100.00
	chip_sw_pwrmgr_smoketest	282.700s	5150.293us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	388.520s	5413.263us	1	1	100.00
	chip_sw_rv_plic_smoketest	265.320s	2634.893us	1	1	100.00
	chip_sw_rv_timer_smoketest	229.680s	3170.757us	1	1	100.00
	chip_sw_rstmgr_smoketest	257.600s	2566.407us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	200.610s	2436.979us	1	1	100.00
	chip_sw_uart_smoketest	266.520s	3025.967us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	197.790s	2385.701us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	465.290s	4814.803us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	20876.090s	126909.277us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3712.820s	14952.777us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	407.650s	8917.724us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	490.200s	3852.150us	1	1	100.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	252.120s	3456.209us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.298s	0.000us	0	1	0.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	3600.154s	0.000us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	3600.154s	0.000us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	7745.730s	70744.441us	1	1	100.00
	chip_same_csr_outstanding	1624.360s	22197.511us	1	1	100.00
	chip_csr_hw_reset	533.900s	10822.716us	1	1	100.00
	chip_csr_rw	435.840s	7299.444us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	7745.730s	70744.441us	1	1	100.00
	chip_same_csr_outstanding	1624.360s	22197.511us	1	1	100.00
	chip_csr_hw_reset	533.900s	10822.716us	1	1	100.00
	chip_csr_rw	435.840s	7299.444us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	23.190s	351.529us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.670s	47.063us	1	1	100.00
	xbar_smoke_large_delays	59.560s	8767.384us	1	1	100.00
	xbar_smoke_slow_rsp	39.800s	3792.382us	1	1	100.00
	xbar_random_zero_delays	9.950s	125.449us	1	1	100.00
	xbar_random_large_delays	133.930s	19479.665us	1	1	100.00
	xbar_random_slow_rsp	34.450s	3544.567us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	7.440s	129.264us	1	1	100.00
	xbar_error_and_unmapped_addr	35.890s	1000.651us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	60.260s	2019.880us	1	1	100.00
	xbar_error_and_unmapped_addr	35.890s	1000.651us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	68.690s	1996.244us	1	1	100.00
	xbar_access_same_device_slow_rsp	152.170s	14656.974us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	13.950s	204.738us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	272.780s	10655.024us	1	1	100.00
	xbar_stress_all_with_error	355.700s	13083.623us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	169.330s	2076.230us	1	1	100.00
	xbar_stress_all_with_reset_error	32.590s	182.490us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3712.820s	14952.777us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3540.750s	30044.939us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3999.430s	20906.607us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2737.330s	11274.672us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3840.450s	16898.574us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3939.200s	15745.366us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3900.990s	15952.331us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3702.430s	15296.760us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2807.370s	11382.204us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3958.150s	15871.466us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3957.070s	17359.008us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3869.260s	17076.481us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3834.840s	15026.542us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5512.170s	17799.816us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	7076.060s	24328.888us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6719.020s	24953.001us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6530.150s	24359.965us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6781.100s	23375.238us	1	1	100.00
rom_e2e_sigverify_always				14	15	93.33
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5427.430s	21736.860us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	7066.070s	31200.785us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6489.690s	31545.198us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6629.780s	30154.694us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6094.330s	22983.093us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3107.620s	16255.138us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3599.940s	18872.382us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	4059.460s	22345.022us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	4191.860s	28460.640us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3668.160s	21239.216us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2609.280s	10371.546us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	4350.520s	25683.066us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3954.970s	30975.910us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	4215.410s	29279.770us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3376.760s	14946.519us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	3004.920s	11228.291us	1	1	100.00
	rom_e2e_asm_init_dev	3800.520s	15614.626us	1	1	100.00
	rom_e2e_asm_init_prod	4293.230s	15924.229us	1	1	100.00
	rom_e2e_asm_init_prod_end	3906.640s	15974.938us	1	1	100.00
	rom_e2e_asm_init_rma	3802.610s	16149.407us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7680.970s	29082.679us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7744.890s	29112.241us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7650.040s	32037.446us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3871.830s	15885.994us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.162s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.162s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	235.970s	2994.125us	1	1	100.00
	chip_sw_aes_enc_jitter_en	208.720s	2294.959us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	253.480s	2807.839us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	200.220s	2364.361us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1084.590s	7756.426us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	191.860s	2538.717us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	511.750s	4676.836us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	629.610s	4461.834us	1	1	100.00
	chip_plic_all_irqs_10	378.250s	3878.122us	1	1	100.00
	chip_plic_all_irqs_20	435.350s	3538.431us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	297.730s	2988.326us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1308.040s	11041.767us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	358.650s	4445.381us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	218.010s	2541.653us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	213.660s	2580.982us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1097.220s	7366.676us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1250.220s	7655.725us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	1107.570s	7697.711us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12200.020s	255120.752us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	311.930s	3626.309us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	282.700s	5150.293us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	311.930s	3626.309us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	602.060s	7913.514us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	602.060s	7913.514us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	462.720s	6371.298us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	394.800s	4020.514us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	711.520s	6142.016us	1	1	100.00
	chip_sw_aes_idle	200.220s	2364.361us	1	1	100.00
	chip_sw_hmac_enc_idle	283.960s	3133.553us	1	1	100.00
	chip_sw_kmac_idle	214.170s	2838.581us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	354.510s	3796.858us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	446.720s	4382.451us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	396.800s	3929.477us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	459.260s	3883.044us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1046.220s	9087.112us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	536.370s	3890.060us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	449.850s	4568.159us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	530.840s	3491.390us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	555.790s	4570.201us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	439.710s	3386.224us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	492.900s	4421.544us	1	1	100.00
	chip_sw_ast_clk_outputs	711.530s	7548.861us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1772.210s	27210.685us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	530.840s	3491.390us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	555.790s	4570.201us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4021.440s	19303.196us	1	1	100.00
	chip_sw_aes_enc_jitter_en	208.720s	2294.959us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	787.810s	6509.683us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	210.000s	3023.493us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1759.260s	11590.168us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	268.210s	3178.854us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	481.740s	4850.707us	1	1	100.00
	chip_sw_clkmgr_jitter	213.810s	2620.688us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	231.440s	2532.403us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4277.510s	25555.828us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	195.630s	2496.939us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	197.110s	2771.229us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	821.340s	7508.060us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	269.940s	3107.036us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	397.140s	4354.952us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	11027.140s	83038.367us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	711.530s	7548.861us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	405.720s	4279.071us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	654.570s	9807.124us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1097.220s	7366.676us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2587.600s	24020.738us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	430.500s	4400.033us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	860.720s	9654.077us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	212.440s	2859.157us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	7609.020s	34728.081us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	243.700s	2813.209us	1	1	100.00
	chip_sw_edn_entropy_reqs	773.490s	5554.637us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	243.700s	2813.209us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2587.600s	24020.738us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	267.790s	2500.780us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	244.330s	2823.719us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	210.000s	3023.493us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	283.960s	3133.553us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1594.460s	8958.352us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2065.330s	12010.160us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	518.610s	5172.425us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	434.380s	4665.768us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	449.010s	4484.184us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	347.040s	3546.131us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	2030.020s	11502.551us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1759.260s	11590.168us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1847.510s	10175.207us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1084.590s	7756.426us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.148s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	252.780s	2975.802us	1	1	100.00
	chip_sw_kmac_mode_kmac	264.950s	3251.915us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	268.210s	3178.854us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2030.020s	11502.551us	1	1	100.00
chip_sw_kmac_app_lc				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	549.980s	9066.179us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1783.300s	9838.584us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	214.170s	2838.581us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	511.750s	4676.836us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	1010.930s	12702.144us	1	1	100.00
	chip_tap_straps_rma	180.930s	3095.854us	1	1	100.00
	chip_tap_straps_prod	144.470s	2556.372us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	209.090s	3192.606us	1	1	100.00
chip_sw_lc_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_lc_ctrl_transitions				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_lc_ctrl_kmac_req				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1965.730s	12698.927us	1	1	100.00
chip_sw_lc_ctrl_broadcast				17	21	80.95
	chip_sw_rram_rma_unlocked	455.050s	10010.260us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	300.730s	3126.029us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	770.980s	6536.310us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	769.300s	6550.270us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	596.930s	5504.970us	0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
	chip_sw_rram_ctrl_lc_rw_en	496.760s	5327.676us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2030.020s	11502.551us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	830.390s	15907.524us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	481.470s	6997.042us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1772.210s	27210.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	536.370s	3890.060us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	449.850s	4568.159us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	530.840s	3491.390us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	555.790s	4570.201us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	439.710s	3386.224us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	492.900s	4421.544us	1	1	100.00
	chip_tap_straps_dev	1010.930s	12702.144us	1	1	100.00
	chip_tap_straps_rma	180.930s	3095.854us	1	1	100.00
	chip_tap_straps_prod	144.470s	2556.372us	1	1	100.00
	chip_rv_dm_lc_disabled	151.030s	4845.525us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	381.740s	5058.669us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	601.650s	9721.730us	0	1	0.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	595.130s	9739.197us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	427.760s	5994.832us	1	1	100.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	2921.560s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	151.030s	4845.525us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1662.840s	18857.408us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1807.980s	18774.470us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1244.100s	15031.431us	1	1	100.00
	chip_sw_lc_walkthrough_rma	1234.910s	15414.582us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2921.560s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	208.910s	5763.053us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	262.460s	5635.499us	1	1	100.00
	rom_volatile_raw_unlock	215.140s	4249.382us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4078.480s	17595.218us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4021.440s	19303.196us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	711.520s	6142.016us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	711.520s	6142.016us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	711.520s	6142.016us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	438.630s	3421.971us	1	1	100.00
chip_otp_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	438.630s	3421.971us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2030.020s	11502.551us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	401.060s	4273.508us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.157s	0.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	438.630s	3421.971us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2030.020s	11502.551us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	401.060s	4273.508us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.157s	0.000us	0	1	0.00
chip_sw_otp_ctrl_program				0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	588.000s	6165.765us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	209.090s	3192.606us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				3	5	60.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	300.730s	3126.029us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	770.980s	6536.310us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	769.300s	6550.270us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	596.930s	5504.970us	0	1	0.00
	chip_sw_lc_ctrl_transition	1028.300s	26482.419us	0	1	0.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1050.440s	7366.879us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	351.750s	6417.998us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	209.400s	3156.315us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	173.710s	2848.632us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	455.550s	7222.077us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	352.000s	4880.343us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	874.400s	20169.552us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	876.380s	14953.405us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	602.060s	7913.514us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	246.580s	3217.708us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	489.330s	4899.330us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	351.750s	6417.998us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	459.240s	4348.978us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	423.120s	6636.087us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	350.480s	6319.088us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	262.900s	3270.844us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	576.550s	7410.442us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	808.340s	6215.321us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1363.160s	12725.224us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1298.730s	18918.840us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	214.940s	2658.110us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	830.390s	15907.524us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	830.390s	15907.524us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1363.160s	12725.224us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	576.550s	7410.442us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	489.330s	4899.330us	1	1	100.00
	chip_sw_pwrmgr_smoketest	282.700s	5150.293us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	355.030s	4258.443us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	417.620s	3934.298us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	366.380s	4407.197us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1308.040s	11041.767us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	218.840s	2443.099us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1250.220s	7655.725us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	598.190s	4534.306us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	649.620s	4844.091us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	223.070s	3173.248us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.157s	0.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	417.620s	3934.298us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	417.620s	3934.298us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	240.560s	3261.074us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	747.760s	11284.996us	1	1	100.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	133.700s	2575.988us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	355.030s	4258.443us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	260.410s	2540.569us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	239.480s	2653.411us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	180.930s	3095.854us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	151.030s	4845.525us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	629.610s	4461.834us	1	1	100.00
	chip_plic_all_irqs_10	378.250s	3878.122us	1	1	100.00
	chip_plic_all_irqs_20	435.350s	3538.431us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	181.430s	3037.494us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	238.530s	3459.547us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3712.820s	14952.777us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	377.490s	4550.132us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	312.940s	3668.990us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	257.090s	3045.179us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	236.200s	2564.288us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	401.060s	4273.508us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	481.740s	4850.707us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	252.140s	2819.333us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	289.260s	3088.174us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	481.470s	6997.042us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
	chip_sw_data_integrity_escalation	550.230s	4933.505us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	808.340s	6215.321us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1239.000s	23494.303us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	194.620s	2895.499us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	352.090s	3943.627us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	414.010s	4205.967us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1239.000s	23494.303us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1239.000s	23494.303us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2868.800s	21080.908us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2868.800s	21080.908us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	410.290s	5742.797us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.162s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	230.230s	2718.351us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	253.000s	2935.938us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	355.530s	3763.194us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	419.520s	3771.197us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1044.070s	7852.303us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6391.670s	31623.006us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2024.220s	12212.152us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	226.870s	2744.038us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	302.310s	2826.250us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	167.600s	2452.334us	1	1	100.00

15/25 passed

60.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	12311.440s	72565.839us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1417.940s	6464.591us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	94.570s	1748.405us	0	1	0.00
	rom_e2e_jtag_debug_dev	98.040s	1990.729us	0	1	0.00
	rom_e2e_jtag_debug_rma	113.680s	1825.620us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	88.810s	1698.432us	0	1	0.00
	rom_e2e_jtag_inject_dev	101.640s	1987.049us	0	1	0.00
	rom_e2e_jtag_inject_rma	112.070s	2333.458us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	139.233s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	320.790s	3285.846us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	412.470s	2776.377us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	566.730s	3365.261us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	788.780s	5225.795us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	301.700s	2252.747us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	219.900s	3088.306us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	309.200s	4954.740us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	324.370s	4167.017us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1363.160s	12725.224us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	549.980s	9066.179us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	94.570s	1748.405us	0	1	0.00
	rom_e2e_jtag_debug_dev	98.040s	1990.729us	0	1	0.00
	rom_e2e_jtag_debug_rma	113.680s	1825.620us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	470.720s	5213.007us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	480.260s	5138.122us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6149.800s	37589.148us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6149.800s	37589.148us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	213.630s	2464.149us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	502.340s	4550.530us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3566.620s	18728.204us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	55.850s	10.200us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	111.730s	2058.372us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	258.800s	3078.753us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	175.290s	3100.140us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.150s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	845.590s	10010.300us	0	1	0.00
	ate_bootstrap_one_frame	10800.158s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.156s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				14 test runs
	chip_sw_sleep_pin_retention	75914503940730790457124990969431286517006026065099433829113198693895543287045	379	UVM_INFO @ 3018.590136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	105071297224139333507738971990708340660385392155285963238115722256470707850542	374	UVM_INFO @ 2464.149016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	41880671028949076138265549028203882062574814687684918101498733668167041406825	392	UVM_INFO @ 7410.441742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	8588940713620823457873523274242414560005832173856837568679329386153054946688	377	UVM_INFO @ 3217.708156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	94641348376158481680043787376623389904548554060900307397737821352346310831738	388	UVM_INFO @ 4880.343398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	58570666542506060272263522502952888303533679840879025535383324393646802519864	377	UVM_INFO @ 2819.332788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	70647576290253954649202868370771365393843746448500392024463673650645238753279	381	UVM_INFO @ 3088.174088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	64137057363618283845368317068097927373695722239171233601931558849121137114998	372	UVM_INFO @ 2912.104456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	79914163394938957144579831077809337956884027930003009817119778082849748757528	407	UVM_INFO @ 4279.071384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	77456871002468523012803304128327035561176390485902471036031915659917774506028	374	UVM_INFO @ 2848.632052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	88029522954823249687969264435154054117151486903496354815141758738363637104104	372	UVM_INFO @ 3100.140036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	27186392203899606552775028070819539106266712968962670965381155588853081397796	373	UVM_INFO @ 3156.315488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	102616048618141713067935197868779459092781789435681232074389954477430179628251	390	UVM_INFO @ 2653.410696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_power_sleep_load	34472658553487249935446589189514194576905434998823227539704483479166637725388	387	UVM_INFO @ 3456.209112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				7 test runs
	chip_sw_exit_test_unlocked_bootstrap	102821730951788448318139494514796970650743308983178732282630873905178679584958	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	35987219371083459396237827812015381725696359626607557045094669862422280759602	None
	chip_sw_keymgr_dpe_sideload_otbn	89287356894132474131095137981153841392599760279015516402305360308099296080725	None
	chip_tl_errors	1423235862513679534309126821926807412700984479790166212817704021252670230052	None
	chip_sw_rv_core_ibex_icache_invalidate	87620683075737873837839962736870821588172468823561725738080267375051244456563	None
	ate_bootstrap_one_frame	39039461314392071275391167102022100591410454484466842113236344262240988878460	None
	ate_bootstrap_disjoint	28461798345078932571005203142077335546311315135563109491065996420170163548834	None
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	14769542615465801429567528922918733350840887559803565346852213690011487233696	383	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	112259222883973040526449254552628426396309618110342286415682168575509947073173	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	84455445750639950469360299429635436323270115190037630349781989642550191798897	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	97576915286422620314243448783565444810605917590977218884800797279841364405399	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	64431420680896019758072580893170045477680570270651745530683189124836464349197	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	23276867412316667186290948866708217084506894977915528638972121572540672687809	433	UVM_INFO @ 18857.408052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	49431905650201472702765875865835953615450655023222265212570187725229584032551	433	UVM_INFO @ 18774.469895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	21884236264989119869120733128694508199005560820864575130821539206978921163881	405	UVM_INFO @ 15414.582182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	79309054664981036169670730827415404760939762322909804850906958500394728570209	359	UVM_INFO @ 1748.405000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	107241871683113394513890132005644314182668122992887363288512801584800665492583	359	UVM_INFO @ 1990.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	74119994403740038407617870934043466288198497534689772965436859620512077203717	359	UVM_INFO @ 1825.619500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_raw_to_scrap	38833222896740730837361857700125813932753427946343161012450939893680667887010	375	UVM_INFO @ 9721.730025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_test_locked0_to_scrap	32608168934962100650904652546478242181859471514707979808558097228578940556991	375	UVM_INFO @ 9739.197057 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	26728913865398970005105485344006478094094016440323394526169957289871542479368	377	UVM_ERROR @ 3270.843610 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3270.843610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	42329472899282556563742505675010867824273223831767870163753827617959298708546	392	UVM_ERROR @ 6636.087288 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 6636.087288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	52700733439800898927758656847011693006236878771958365641285975645523386610998	374	UVM_INFO @ 2580.982152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	36873220525104111342138016039110021842058049563683789813689270442671502197265	490	UVM_INFO @ 2988.325704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	19686819517272649844960151849002274674865761256538913561673277211442457021001	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	99021116046991561940687511963241838743768256825730154933957444270416571426623	None	Another command (pid=483632) is running. Waiting for it to complete on the server (server_pid=222521)... Another command (pid=449788) is running. Waiting for it to complete on the server (server_pid=222521)... Another command (pid=485034) is running. Waiting for it to complete on the server (server_pid=222521)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	69189475334132659768239258115637174595703269666991215275218865727872419497570	365	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	87374314037062418784292437213119691322711304846605095128063732845618399011546	391	UVM_INFO @ 3668.990440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	75674595663872279393009063739213863502050329049301897471894055407899369939389	337	UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	84990245823110591954850892932052342727213860888556830325891414665586401438856	404	UVM_INFO @ 5504.969744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	104405867920479163390221006620619072235151758121491318938468060398640771583155	380	UVM_ERROR @ 3088.306296 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3088.306296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_transition	14481146961041667383891484162803510156435970036379930606276198905120670821511	369	UVM_INFO @ 26482.418951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				1 test run
	chip_sw_lc_walkthrough_testunlocks	95612858067747243477863337182063046332096112579510197139356705002791299443474	513	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	55049394822575513276585916059303820376858235037504813213506082233867710604952	371	UVM_INFO @ 2538.717217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	101147461425907614773139828998810067551360462959991312892484175211749941873949	373	UVM_INFO @ 2541.652675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	104075451092411203810396343596354419644996569112051053219876991951064560719061	429	UVM_INFO @ 12010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	110979700978600983114174184901996493226864258429584650040405344727764172057446	400	UVM_INFO @ 9807.124150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	112276573429722804863751897476857177299739649357396738227207213271151366713451	407	UVM_INFO @ 3285.846322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_mem_access	107413543576677444386395464315675464852768485150353083772591521829936732594986	5365	UVM_INFO @ 2575.988370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [] vs []) RV_DM sbaddress read back check failed, got , expected				1 test run
	chip_rv_dm_lc_disabled	37536911487880604718384669584456051384325729229418904033604950510016791549076	314	UVM_INFO @ 4845.525480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIoc* (num=27)				1 test run
	chip_padctrl_attributes	103223899509022747007843038610939117338248275936814104732048977441545117710312	349	UVM_INFO @ 2401.104253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	85707509678946243613683660589637471260190540456919888873867361199369178238640	391	UVM_INFO @ 11378.490290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	85713241764166987062854001242458302380316202477290805674929184382664631480602	339	UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	20151420229595108722552861529805375551380264683201794186728209081008844655754	406	UVM_ERROR @ 30975.910119 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 30975.910119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	rom_raw_unlock	36608261077353329446208085114555264153020705997807267868977180079253958114795	384	UVM_INFO @ 8917.724488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---