Simulation Results: clkmgr

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.66 %
  • code
  • 97.13 %
  • assert
  • 92.94 %
  • func
  • 84.91 %
  • line
  • 98.62 %
  • branch
  • 98.02 %
  • cond
  • 89.83 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.120s 28.822us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 14.803us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.910s 283.598us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.150s 39.104us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.950s 23.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
clkmgr_csr_aliasing 1.150s 39.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.950s 17.437us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.260s 27.793us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.030s 18.562us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.820s 15.724us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.120s 28.822us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 16.180s 1877.153us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 14.260s 2181.370us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 16.180s 1877.153us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 13.100s 4744.061us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.920s 14.688us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.540s 445.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.540s 445.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 14.803us 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
clkmgr_csr_aliasing 1.150s 39.104us 1 1 100.00
clkmgr_same_csr_outstanding 1.960s 156.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 14.803us 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
clkmgr_csr_aliasing 1.150s 39.104us 1 1 100.00
clkmgr_same_csr_outstanding 1.960s 156.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.090s 20.383us 0 1 0.00
clkmgr_tl_intg_err 2.020s 77.794us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 520.600s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 520.600s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 520.600s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 520.600s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.230s 59.156us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.020s 77.794us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 16.180s 1877.153us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 14.260s 2181.370us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 520.600s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.860s 171.197us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.130s 27.633us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.190s 60.661us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.940s 26.144us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.260s 31.121us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.090s 20.383us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.270s 90.972us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.090s 20.383us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.860s 541.742us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 69.450s 17234.027us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 7057564126170711749517575306042841051327629729898747506990119981508548641939 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 25880559823024322277289924226789277345583903484591361992270319358045260577561 81
UVM_INFO @ 59155911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 17934023920807821362651614871945037877086144890979123527095769797218661290243 99
UVM_INFO @ 20382633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---